[PATCH 06/13] RISC-V: Add T-Head CondMov vendor extension
Christoph Muellner
christoph.muellner@vrull.eu
Tue Sep 6 12:22:06 GMT 2022
From: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 3 +++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/x-thead-condmov.d | 11 +++++++++++
gas/testsuite/gas/riscv/x-thead-condmov.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
7 files changed, 35 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c12a328505c..d5e8a40a751 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1227,6 +1227,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -2398,6 +2399,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xtheadbs");
case INSN_CLASS_XTHEADCMO:
return riscv_subset_supports (rps, "xtheadcmo");
+ case INSN_CLASS_XTHEADCONDMOV:
+ return riscv_subset_supports (rps, "xtheadcondmov");
case INSN_CLASS_XTHEADSYNC:
return riscv_subset_supports (rps, "xtheadsync");
default:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 570a4f467f8..b1462ce213b 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -724,6 +724,11 @@ The XTheadCmo extension provides instructions for cache management.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+@item XTheadCondMov
+The XTheadCondMov extension provides instructions for conditional moves.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
@item XTheadSync
The XTheadSync extension provides instructions for multi-processor synchronization.
diff --git a/gas/testsuite/gas/riscv/x-thead-condmov.d b/gas/testsuite/gas/riscv/x-thead-condmov.d
new file mode 100644
index 00000000000..5972d09ec99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-condmov.d
@@ -0,0 +1,11 @@
+#as: -march=rv64i_xtheadcondmov
+#source: x-thead-condmov.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+40c5950b[ ]+th.mveqz[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+42c5950b[ ]+th.mvnez[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/x-thead-condmov.s b/gas/testsuite/gas/riscv/x-thead-condmov.s
new file mode 100644
index 00000000000..f71191d110b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-condmov.s
@@ -0,0 +1,3 @@
+target:
+ th.mveqz a0, a1, a2
+ th.mvnez a0, a1, a2
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9ed5cb455f2..5c0f6100e29 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2181,6 +2181,11 @@
#define MASK_TH_L2CACHE_CIALL 0xffffffff
#define MATCH_TH_L2CACHE_IALL 0x0160000b
#define MASK_TH_L2CACHE_IALL 0xffffffff
+/* Vendor-specific (T-Head) XTheadCondMov instructions. */
+#define MATCH_TH_MVEQZ 0x4000100b
+#define MASK_TH_MVEQZ 0xfe00707f
+#define MATCH_TH_MVNEZ 0x4200100b
+#define MASK_TH_MVNEZ 0xfe00707f
/* Vendor-specific (T-Head) XTheadSync instructions. */
#define MATCH_TH_SFENCE_VMAS 0x0400000b
#define MASK_TH_SFENCE_VMAS 0xfe007fff
@@ -2967,6 +2972,9 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA)
DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL)
DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL)
DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
+/* Vendor-specific (T-Head) XTheadCondMov instructions. */
+DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ)
+DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ)
/* Vendor-specific (T-Head) XTheadSync instructions. */
DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 53b5b3c5aaf..d0ff929f84b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -419,6 +419,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
INSN_CLASS_XTHEADCMO,
+ INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADSYNC,
};
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6f4a3f8236c..111308686fc 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1867,6 +1867,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0},
{"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0},
+/* Vendor-specific (T-Head) XTheadCondMov instructions. */
+{"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0},
+{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadSync instructions. */
{"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0},
{"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0},
--
2.37.2
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