[PATCH 10/10] Support Intel PREFETCHI

[Jan Beulich]

On 25.10.2022 09:49, Cui, Lili wrote:
>> On 19.10.2022 17:15, Haochen Jiang wrote:
>>> --- a/gas/config/tc-i386.c
>>> +++ b/gas/config/tc-i386.c
>>> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
>>>    SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
>>>    SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
>>>    SUBARCH (msrlist, MSRLIST, MSRLIST, false),
>>> +  SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
>>>  };
>>>
>>>  #undef SUBARCH
>>> @@ -4522,7 +4523,8 @@ load_insn_p (void)
>>>      {
>>>        /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
>>>  	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
>>> -	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
>>> +	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
>>> +	 prefetchit1.  */
>>>        if (i.tm.opcode_modifier.anysize)
>>>  	return 0;
>>>
>>
>> There's still no change in this file making sure that the new insns are _only_
>> accepted with RIP-relative addressing. See my earlier comments.
>>
> I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.

Personally I think a warning is too little, but if H.J. agrees with you,
then so be it.

Jan