[PATCH 06/10] Support Intel RAO-INT

[Jan Beulich]

On 18.10.2022 01:23, H.J. Lu wrote:
> On Fri, Oct 14, 2022 at 2:15 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
>>  cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>>
>>  // CMPCCXADD instructions end.
>> +
>> +// RAOINT instructions.
>> +
>> +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> 
> l and q suffixes are allowed.  Personally, I think l and q suffixes
> should be used
> only when they are needed in some forms.

As said elsewhere (repeating here mainly for the authors' sake): The
spirit of the only AT&T doc I'm aware of looks to be to mandate use of
suffixes wherever sized memory operands are involved (non-sized ones
would e.g. be those used by PREFETCH*). Plus disallowing their use
(also relevant for CMPccXADD) introduces inconsistencies.

Jan