[PATCH 04/10] Support Intel CMPccXADD

[Jan Beulich]

On 14.10.2022 20:27, H.J. Lu wrote:
>  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
>>>  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>>>
>>>  // AVX_VNNI_INT8 instructions end.
>>> +
>>> +// CMPCCXADD instructions.
>>> +
>>> +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>>
>> Along the lines of the earlier comment - you want to use the <cc>
>> template here, eliminating the need for 16 almost identical lines _and_
>> supplying all condition code representation in one go.
>>
>> Apart from that you forgot CheckRegSize here afaict. And please again
>> VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
>> Vex instead of Vex128. Further these insns should allow for l and q
>> suffixes in AT&T mode.
> 
> l and q suffixes here are totally unnecessary.  For new instructions,
> suffixes should be required only if needed.

I disagree, and I'd like to ask that decisions like this not be made behind
closed doors at Intel. As said many times - there needs to be consistency,
which is a prereq for predictability. A programmer shall not be required to
read gas sources to know for which insns suffixes are permitted and for
which they aren't. Plus do you realize that "new insns" also covers RAO-INT,
where suffixes are permitted (as expected)?

Jan