[PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers

[Jeff Law]

On 10/2/22 19:36, Nelson Chu wrote:
> On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
> <binutils@sourceware.org> wrote:
>> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
>>> I can't approve binutils patches, but as this mentioned RISC-V and
>>> DWARF, both of which I'm interested in, I took a look :)
>>>
>>> Both these patches look good to me.  The register numbers align with the
>>> spec, and the test makes sense.
>> Well, that's the key property -- they align with the spec.
>>
>>
>> I'm also not sure if I can approve for binutils, but if I can, OK for
>> the trunk ;-)
> Thanks for your help, Andrew and Jeff!
>
> Hi Jeff,
>
> Of course!  You are a global maintainer of both gcc and binutils.
> Welcome and please feel free to approve any RISC-V binutils patch if
> you are free and the patch looks good to you :-)

I may be listed as a global maintainer for binutils, but I haven't done 
much in this space in years and I'm cognizant that there's already a 
group of folks (yourself included) working together on RISC-V bits.   I 
don't want to step on anyones toes, but I also want to help share the load.


Jeff