[REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
Palmer Dabbelt
palmer@dabbelt.com
Tue Nov 29 02:38:57 GMT 2022
On Mon, 28 Nov 2022 18:19:31 PST (-0800), research_trasio@irq.a4lg.com wrote:
> On 2022/11/29 10:41, Palmer Dabbelt wrote:
>> On Mon, 28 Nov 2022 17:16:56 PST (-0800), binutils@sourceware.org wrote:
>>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>>
>>> [DO NOT MERGE]
>>> Until 'ZiCondOps' extension is frozen/ratified and final version
>>> number is
>>> determined, this patch should not be merged upstream. This commit uses
>>> version 1.0 as in the documentation.
>>>
>>> This commit adds support for the latest draft of RISC-V Integer
>>> Conditional
>>> Operations (ZiCondOps) extension consisting of 2 new instructions.
>>>
>>> This is based on the early draft of ZiCondOps on GitHub:
>>> <https://github.com/riscv/riscv-zicondops/commit/91e173db867875a6e0ab21c89d146f1a28f416e3>
>>>
>>> bfd/ChangeLog:
>>>
>>> * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
>>> (riscv_multi_subset_supports): Support new instruction class.
>>> (riscv_multi_subset_supports_ext): Likewise.
>>>
>>> gas/ChangeLog:
>>>
>>> * testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
>>> * testsuite/gas/riscv/zicondops.d: Likewise.
>>> * testsuite/gas/riscv/zicondops-noarch.d: New test for
>>> architecture failure.
>>> * testsuite/gas/riscv/zicondops-noarch.l: Likewise.
>>>
>>> include/ChangeLog:
>>>
>>> * opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
>>> MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
>>> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
>>> class INSN_CLASS_ZICONDOPS.
>>>
>>> opcodes/ChangeLog:
>>>
>>> * riscv-opc.c (riscv_opcodes): Add new instructions from the
>>> 'ZiCondOps' extension.
>>> ---
>>> bfd/elfxx-riscv.c | 5 +++++
>>> gas/testsuite/gas/riscv/zicondops-noarch.d | 3 +++
>>> gas/testsuite/gas/riscv/zicondops-noarch.l | 3 +++
>>> gas/testsuite/gas/riscv/zicondops.d | 11 +++++++++++
>>> gas/testsuite/gas/riscv/zicondops.s | 3 +++
>>> include/opcode/riscv-opc.h | 8 ++++++++
>>> include/opcode/riscv.h | 1 +
>>> opcodes/riscv-opc.c | 4 ++++
>>> 8 files changed, 38 insertions(+)
>>> create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
>>> create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
>>> create mode 100644 gas/testsuite/gas/riscv/zicondops.d
>>> create mode 100644 gas/testsuite/gas/riscv/zicondops.s
>>>
>>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>>> index 0bcf2fdcfa34..564fef205d01 100644
>>> --- a/bfd/elfxx-riscv.c
>>> +++ b/bfd/elfxx-riscv.c
>>> @@ -1168,6 +1168,7 @@ static struct riscv_supported_ext
>>> riscv_supported_std_z_ext[] =
>>> {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>>> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>>> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>>> + {"zicondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>>> {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>>> {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>>> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>>> @@ -2318,6 +2319,8 @@ riscv_multi_subset_supports
>>> (riscv_parse_subset_t *rps,
>>> return riscv_subset_supports (rps, "zicbop");
>>> case INSN_CLASS_ZICBOZ:
>>> return riscv_subset_supports (rps, "zicboz");
>>> + case INSN_CLASS_ZICONDOPS:
>>> + return riscv_subset_supports (rps, "zicondops");
>>> case INSN_CLASS_ZICSR:
>>> return riscv_subset_supports (rps, "zicsr");
>>> case INSN_CLASS_ZIFENCEI:
>>> @@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext
>>> (riscv_parse_subset_t *rps,
>>> return "zicbop";
>>> case INSN_CLASS_ZICBOZ:
>>> return "zicboz";
>>> + case INSN_CLASS_ZICONDOPS:
>>> + return "zicondops";
>>> case INSN_CLASS_ZICSR:
>>> return "zicsr";
>>> case INSN_CLASS_ZIFENCEI:
>>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> b/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> new file mode 100644
>>> index 000000000000..4f01b10f42df
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> @@ -0,0 +1,3 @@
>>> +#as: -march=rv32i
>>> +#source: zicondops.s
>>> +#error_output: zicondops-noarch.l
>>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> b/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> new file mode 100644
>>> index 000000000000..b665d6022b98
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> @@ -0,0 +1,3 @@
>>> +.*: Assembler messages:
>>> +.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension
>>> `zicondops' required
>>> +.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension
>>> `zicondops' required
>>> diff --git a/gas/testsuite/gas/riscv/zicondops.d
>>> b/gas/testsuite/gas/riscv/zicondops.d
>>> new file mode 100644
>>> index 000000000000..9f417fa3b5ea
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops.d
>>> @@ -0,0 +1,11 @@
>>> +#as: -march=rv32i_zicondops
>>> +#source: zicondops.s
>>> +#objdump: -d
>>> +
>>> +.*:[ ]+file format .*
>>> +
>>> +Disassembly of section .text:
>>> +
>>> +0+000 <target>:
>>> +[ ]+[0-9a-f]+:[ ]+80c5a533[ ]+czero\.eqz[ ]+a0,a1,a2
>>> +[ ]+[0-9a-f]+:[ ]+80f736b3[ ]+czero\.nez[ ]+a3,a4,a5
>>> diff --git a/gas/testsuite/gas/riscv/zicondops.s
>>> b/gas/testsuite/gas/riscv/zicondops.s
>>> new file mode 100644
>>> index 000000000000..dcf3d98ccd7e
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops.s
>>> @@ -0,0 +1,3 @@
>>> +target:
>>> + czero.eqz a0, a1, a2
>>> + czero.nez a3, a4, a5
>>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>>> index 06e3df0f5a63..ea38df13ce6d 100644
>>> --- a/include/opcode/riscv-opc.h
>>> +++ b/include/opcode/riscv-opc.h
>>> @@ -2113,6 +2113,11 @@
>>> #define MASK_CBO_INVAL 0xfff07fff
>>> #define MATCH_CBO_ZERO 0x40200f
>>> #define MASK_CBO_ZERO 0xfff07fff
>>> +/* ZiCondOps instructions. */
>>> +#define MATCH_CZERO_EQZ 0x80002033
>>> +#define MASK_CZERO_EQZ 0xfe00707f
>>> +#define MATCH_CZERO_NEZ 0x80003033
>>> +#define MASK_CZERO_NEZ 0xfe00707f
>>> /* Zawrs intructions. */
>>> #define MATCH_WRS_NTO 0x00d00073
>>> #define MASK_WRS_NTO 0xffffffff
>>> @@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN,
>>> MASK_CBO_CLEAN);
>>> DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
>>> DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
>>> DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
>>> +/* ZiCondOps instructions. */
>>> +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
>>> +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
>>> /* Zawrs instructions. */
>>> DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
>>> DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>>> index c3cbde600cb0..c482f6f4d9f2 100644
>>> --- a/include/opcode/riscv.h
>>> +++ b/include/opcode/riscv.h
>>> @@ -375,6 +375,7 @@ enum riscv_insn_class
>>> INSN_CLASS_Q,
>>> INSN_CLASS_F_AND_C,
>>> INSN_CLASS_D_AND_C,
>>> + INSN_CLASS_ZICONDOPS,
>>> INSN_CLASS_ZICSR,
>>> INSN_CLASS_ZIFENCEI,
>>> INSN_CLASS_ZIHINTPAUSE,
>>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>>> index 0e691544f9bc..311df46daa2d 100644
>>> --- a/opcodes/riscv-opc.c
>>> +++ b/opcodes/riscv-opc.c
>>> @@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
>>> {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL,
>>> MASK_CBO_INVAL, match_opcode, 0 },
>>> {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO,
>>> MASK_CBO_ZERO, match_opcode, 0 },
>>>
>>> +/* ZiCondOps instructions. */
>>> +{"czero.eqz", 0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ,
>>> MASK_CZERO_EQZ, match_opcode, 0 },
>>> +{"czero.nez", 0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ,
>>> MASK_CZERO_NEZ, match_opcode, 0 },
>>> +
>>> /* Zawrs instructions. */
>>> {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO,
>>> match_opcode, 0 },
>>> {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO,
>>> match_opcode, 0 },
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze
>>
>> Thanks!
>>
>
> Thanks for reviewing this but I found that the encodings of those
> instruction have changed just a few hours ago. I will notify that I've
> submitted REVIEW ONLY v2 patchset for this.
>
> <https://sourceware.org/pipermail/binutils/2022-November/124768.html>
Thanks. That kind of stuff tends to move around a lot before the opcode
folks commit to an allocation, so it's probably best waiting until that
happens before trying too hard to track the encodings -- otherwise
you're likely to just loose your mind ;)
>
> Thanks,
> Tsukasa
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