[PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard

[zengxiao@eswincomputing.com]

From: Xiao Zeng <zengxiao@eswincomputing.com>

The R_RISCV_SUB6 only the lower 6 bits of the code are valid, which
can be found in 8.5. Relocations of:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf

bfd/ChangeLog:

        * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
	lower 6 bits as the significant bit.
        * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
---
 bfd/elfnn-riscv.c | 4 ++++
 bfd/elfxx-riscv.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 0570a971b5a..a02aa64786e 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -2427,6 +2427,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	  break;
 
 	case R_RISCV_SUB6:
+	  relocation = (old_value & ~howto->dst_mask)
+		       | (((old_value & howto->dst_mask) - relocation)
+			  & howto->dst_mask);
+	  break;
 	case R_RISCV_SUB8:
 	case R_RISCV_SUB16:
 	case R_RISCV_SUB32:
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index afbde56b9e5..2db24acf7a5 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
       relocation = old_value + relocation;
       break;
     case R_RISCV_SUB6:
+      relocation = (old_value & ~howto->dst_mask)
+		    | (((old_value & howto->dst_mask) - relocation)
+		      & howto->dst_mask);
+      break;
     case R_RISCV_SUB8:
     case R_RISCV_SUB16:
     case R_RISCV_SUB32:
-- 
2.34.1