[PATCH 2/2] Support Intel AVX-NE-CONVERT

[Jan Beulich]

On 01.11.2022 02:24, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Monday, October 31, 2022 5:15 PM
>>
>> On 31.10.2022 07:06, Haochen Jiang wrote:
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16,
>>> Modrm|Space0F38|VexVVVV|Masking=3|VexW0
>>>
>>>  // AVX512_BF16 instructions end.
>>>
>>> +// AVX-NE-CONVERT instructions.
>>> +
>>> +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
>> vbcstnesh2ps,
>>> +0x66b1, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
>> vcvtneebf162ps,
>>> +0xf3b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>
>> There's still no CheckRegSize for these last four.
> 
> Sorry for not mention that. I checked code and I suppose if we are using one
> memory operand and one register operand, CheckRegSize seems like doing
> nothing since the check function will return 1 for memory operand.

A comment ahead of the function specifically says "Some Intel syntax memory
operand size checking also happens here." And as I've said earlier on - if
that for some reason doesn't work here, it needs fixing. The only criteria
that's relevant here is whether mismatched operands like in

	vcvtneoph2ps xmm, ymmword ptr [rax]
	vcvtneoph2ps ymm, xmmword ptr [rax]

are properly rejected.

Jan