[PATCH 4/5] PowerPC SPE/SPE2 aliases in powerpc_macros
Alan Modra
amodra@gmail.com
Tue Mar 15 23:40:58 GMT 2022
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs",
"evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt",
"evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui",
"evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz",
"evststgt", "evststlt", "evststeq"..
(powerpc_opcodes): ..to here.
(powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi",
and "evdotpwsssia"..
(spe2_opcodes): ..to here.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 12c1c414b7d..df0d5417d23 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5254,48 +5254,71 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
@@ -10495,36 +10518,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-/* old SPE instructions have new names with the same opcodes */
-{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
-{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
-{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"},
-{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"},
-{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"},
-{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"},
-{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"},
-{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"},
-{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"},
-{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"},
-{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"},
-{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"},
-{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"},
-{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"},
-{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"},
-{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"},
-{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"},
-{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"},
-{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"},
-{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"},
-{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"},
-{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"},
-{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"},
-
-/* SPE2 instructions which just are mapped to SPE2 */
-{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"},
-{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"},
-{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"},
-{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"}
};
const int powerpc_num_macros =
@@ -10622,6 +10615,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10645,6 +10639,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10717,6 +10712,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10732,6 +10728,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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