[PATCH v5 5/7] ppc/svp64: support svshape instruction

[Dmitry Selyutin]

https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svshape
https://libre-soc.org/openpower/isa/simplev/
---
 gas/testsuite/gas/ppc/ppc.exp   |  1 +
 gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++
 gas/testsuite/gas/ppc/svshape.s |  5 +++++
 opcodes/ppc-opc.c               | 23 +++++++++++++++++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 gas/testsuite/gas/ppc/svshape.d
 create mode 100644 gas/testsuite/gas/ppc/svshape.s

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
 
 run_dump_test "setvl"
 run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..8244741ed3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:	(19 00 e0 5b|5b e0 00 19) 	svshape 32,1,1,0,0
+.*:	(19 00 1f 58|58 1f 00 19) 	svshape 1,32,1,0,0
+.*:	(19 f8 00 58|58 00 f8 19) 	svshape 1,1,32,0,0
+.*:	(99 07 00 58|58 00 07 99) 	svshape 1,1,1,15,0
+.*:	(59 00 00 58|58 00 00 59) 	svshape 1,1,1,0,1
diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..c83373ba37
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,5 @@
+svshape 32,1,1,0,0
+svshape 1,32,1,0,0
+svshape 1,1,32,0,0
+svshape 1,1,1,15,0
+svshape 1,1,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 60a038aa40..f95bbf9402 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define ms vs + 1
   { 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+  { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+  { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVyd SVxd + 1
+  { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVzd SVyd + 1
+  { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVrm SVzd + 1
+  { 0xf, 7, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4714,6 +4729,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(rc)) & 1))
 #define SVL_MASK	SVL (0x3f, 0x1f, 1)
 
+/* An SVM form instruction. */
+#define SVM(op, xop)				\
+  (OP (op)					\
+   | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK	SVM (0x3f, 0x3f)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -6786,6 +6807,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"svstep",	SVL(22,19,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
 {"svstep.",	SVL(22,19,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
 
+{"svshape",	SVM(22,25),	SVM_MASK,	SVP64,	PPCVLE,	{SVxd, SVyd, SVzd, SVrm, vf}},
+
 {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 {"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 
-- 
2.36.1