[PATCH] RISC-V: Add cmobase instruction support
Jan Beulich
jbeulich@suse.com
Tue Jan 11 08:28:19 GMT 2022
On 11.01.2022 09:22, Christoph Muellner via Binutils wrote:
> This patch adds support for the recently ratified cmobase instructions,
> grouped into the extensions zicbom, zicbop, and zicboz.
Would you mind clarifying how this correlates with the earlier submission
with the same purpose:
https://sourceware.org/pipermail/binutils/2021-December/118909.html
Jan
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add zicbom,
> zicbop, and zicboz.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/cmobase-64.d: New test.
> * testsuite/gas/riscv/cmobase-64.s: New test.
> * testsuite/gas/riscv/cmobase.d: New test.
> * testsuite/gas/riscv/cmobase.s: New test.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_CBO_INVAL): New define.
> (MASK_CBO_INVAL): New define.
> (MATCH_CBO_CLEAN): New define.
> (MASK_CBO_CLEAN): New define.
> (MATCH_CBO_FLUSH): New define.
> (MASK_CBO_FLUSH): New define.
> (MATCH_PREFETCH_R): New define.
> (MASK_PREFETCH_R): New define.
> (MATCH_PREFETCH_W): New define.
> (MASK_PREFETCH_W): New define.
> (MATCH_PREFETCH_I): New define.
> (MASK_PREFETCH_I): New define.
> (MATCH_CBO_ZERO): New define.
> (MASK_CBO_ZERO): New define.
> (DECLARE_INSN): Declaration of cbo* and prefetch* instructions.
> * opcode/riscv.h (enum riscv_insn_class): Added
> INSN_CLASS_ZICBO*.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c: Add cbo* and prefetch* instructions.
>
> Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
> ---
> bfd/elfxx-riscv.c | 9 +++++++
> gas/testsuite/gas/riscv/cmobase-64.d | 21 +++++++++++++++++
> gas/testsuite/gas/riscv/cmobase-64.s | 10 ++++++++
> gas/testsuite/gas/riscv/cmobase.d | 21 +++++++++++++++++
> gas/testsuite/gas/riscv/cmobase.s | 10 ++++++++
> include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-opc.c | 13 +++++++++++
> 8 files changed, 122 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/cmobase-64.d
> create mode 100644 gas/testsuite/gas/riscv/cmobase-64.s
> create mode 100644 gas/testsuite/gas/riscv/cmobase.d
> create mode 100644 gas/testsuite/gas/riscv/cmobase.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 9f52bb545ac..51add9fe005 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1194,6 +1194,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2384,6 +2387,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> case INSN_CLASS_ZBC_OR_ZBKC:
> return (riscv_subset_supports (rps, "zbc")
> || riscv_subset_supports (rps, "zbkc"));
> + case INSN_CLASS_ZICBOM:
> + return riscv_subset_supports (rps, "zicbom");
> + case INSN_CLASS_ZICBOP:
> + return riscv_subset_supports (rps, "zicbop");
> + case INSN_CLASS_ZICBOZ:
> + return riscv_subset_supports (rps, "zicboz");
> case INSN_CLASS_ZKND:
> return riscv_subset_supports (rps, "zknd");
> case INSN_CLASS_ZKNE:
> diff --git a/gas/testsuite/gas/riscv/cmobase-64.d b/gas/testsuite/gas/riscv/cmobase-64.d
> new file mode 100644
> index 00000000000..0410a946e84
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cmobase-64.d
> @@ -0,0 +1,21 @@
> +#as: -march=rv64i_zicbom_zicbop_zicboz
> +#source: cmobase.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target_zicbom>:
> +[ ]+0:[ ]+0015200f[ ]+cbo.clean[ ]+a0
> +[ ]+4:[ ]+0025200f[ ]+cbo.flush[ ]+a0
> +[ ]+8:[ ]+0005200f[ ]+cbo.inval[ ]+a0
> +
> +0+00c <target_zicbop>:
> +[ ]+c:[ ]+00056013[ ]+prefetch.i[ ]+0\(a0\)
> +[ ]+10:[ ]+00156013[ ]+prefetch.r[ ]+0\(a0\)
> +[ ]+14:[ ]+00356013[ ]+prefetch.w[ ]+0\(a0\)
> +
> +0+018 <target_zicboz>:
> +[ ]+18:[ ]+0045200f[ ]+cbo.zero[ ]+a0
> diff --git a/gas/testsuite/gas/riscv/cmobase-64.s b/gas/testsuite/gas/riscv/cmobase-64.s
> new file mode 100644
> index 00000000000..b5e2a9f72b7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cmobase-64.s
> @@ -0,0 +1,10 @@
> +target_zicbom:
> + cbo.clean a0
> + cbo.flush a0
> + cbo.inval a0
> +target_zicbop:
> + prefetch.i 0(a0)
> + prefetch.r 0(a0)
> + prefetch.w 0(a0)
> +target_zicboz:
> + cbo.zero a0
> diff --git a/gas/testsuite/gas/riscv/cmobase.d b/gas/testsuite/gas/riscv/cmobase.d
> new file mode 100644
> index 00000000000..24f594ed4f4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cmobase.d
> @@ -0,0 +1,21 @@
> +#as: -march=rv32i_zicbom_zicbop_zicboz
> +#source: cmobase.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target_zicbom>:
> +[ ]+0:[ ]+0015200f[ ]+cbo.clean[ ]+a0
> +[ ]+4:[ ]+0025200f[ ]+cbo.flush[ ]+a0
> +[ ]+8:[ ]+0005200f[ ]+cbo.inval[ ]+a0
> +
> +0+00c <target_zicbop>:
> +[ ]+c:[ ]+00056013[ ]+prefetch.i[ ]+0\(a0\)
> +[ ]+10:[ ]+00156013[ ]+prefetch.r[ ]+0\(a0\)
> +[ ]+14:[ ]+00356013[ ]+prefetch.w[ ]+0\(a0\)
> +
> +0+018 <target_zicboz>:
> +[ ]+18:[ ]+0045200f[ ]+cbo.zero[ ]+a0
> diff --git a/gas/testsuite/gas/riscv/cmobase.s b/gas/testsuite/gas/riscv/cmobase.s
> new file mode 100644
> index 00000000000..b5e2a9f72b7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cmobase.s
> @@ -0,0 +1,10 @@
> +target_zicbom:
> + cbo.clean a0
> + cbo.flush a0
> + cbo.inval a0
> +target_zicbop:
> + prefetch.i 0(a0)
> + prefetch.r 0(a0)
> + prefetch.w 0(a0)
> +target_zicboz:
> + cbo.zero a0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 0b8cc6c7ddb..2b085887709 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -521,6 +521,27 @@
> #define MASK_BINV 0xfe00707f
> #define MATCH_BEXT 0x48005033
> #define MASK_BEXT 0xfe00707f
> +
> +/* Zicbom instructions. */
> +#define MATCH_CBO_INVAL 0x0000200f
> +#define MASK_CBO_INVAL 0xfff07fff
> +#define MATCH_CBO_CLEAN 0x0010200f
> +#define MASK_CBO_CLEAN 0xfff07fff
> +#define MATCH_CBO_FLUSH 0x0020200f
> +#define MASK_CBO_FLUSH 0xfff07fff
> +
> +/* Zicbop instructions. */
> +#define MATCH_PREFETCH_R 0x00106013
> +#define MASK_PREFETCH_R 0x01f07fff
> +#define MATCH_PREFETCH_W 0x00306013
> +#define MASK_PREFETCH_W 0x01f07fff
> +#define MATCH_PREFETCH_I 0x00006013
> +#define MASK_PREFETCH_I 0x01f07fff
> +
> +/* Zicboz instructions. */
> +#define MATCH_CBO_ZERO 0x0040200f
> +#define MASK_CBO_ZERO 0xfff07fff
> +
> #define MATCH_FLW 0x2007
> #define MASK_FLW 0x707f
> #define MATCH_FLD 0x3007
> @@ -2548,6 +2569,20 @@ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
> DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
> DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
> DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
> +
> +/* Zicbom instructions. */
> +DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
> +DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
> +DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
> +
> +/* Zicbop instructions. */
> +DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
> +DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
> +DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I);
> +
> +/* Zicboz instructions. */
> +DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
> +
> DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
> DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
> DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 048ab0a5d68..e6696b6934a 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -377,6 +377,9 @@ enum riscv_insn_class
> INSN_CLASS_ZBKB,
> INSN_CLASS_ZBKC,
> INSN_CLASS_ZBKX,
> + INSN_CLASS_ZICBOM,
> + INSN_CLASS_ZICBOP,
> + INSN_CLASS_ZICBOZ,
> INSN_CLASS_ZKND,
> INSN_CLASS_ZKNE,
> INSN_CLASS_ZKNH,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 2da0f7cf0a4..b0fc09dbba1 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -268,6 +268,11 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
>
> const struct riscv_opcode riscv_opcodes[] =
> {
> +/* Zicbop instructions (must be before ori). */
> +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "q(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
> +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "q(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
> +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "q(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
> +
> /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
> {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
> {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
> @@ -920,6 +925,14 @@ const struct riscv_opcode riscv_opcodes[] =
> {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
>
> +/* Zicbom instructions. */
> +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> +
> +/* Zicboz instructions. */
> +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
> +
> /* Zbkx instructions. */
> {"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> {"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
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