[PATCH][GAS][5/8] aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions

[Jan Beulich]

On 25.10.2021 23:09, Przemyslaw Wirkus via Binutils wrote:
> gas/ChangeLog:
> 
>                 * config/tc-aarch64.c (parse_sme_address): New parser.
>                 (parse_sme_za_hv_tiles_operand_with_braces): New parser.
>                 (parse_sme_za_array): New parser.
>                 (output_operand_error_record): Print error details if
>                 present.
>                 (parse_operands): Support new operands.
>                 * testsuite/gas/aarch64/sme-5-illegal.d: New test.
>                 * testsuite/gas/aarch64/sme-5-illegal.l: New test.
>                 * testsuite/gas/aarch64/sme-5-illegal.s: New test.
>                 * testsuite/gas/aarch64/sme-5.d: New test.
>                 * testsuite/gas/aarch64/sme-5.s: New test.

Quoting from this test (again it would be easier to comment if patches
were sent inline):

> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme-5.d
> @@ -0,0 +1,93 @@
> +#name: SME extension (LD1x instructions)
> +#as: -march=armv8-a+sme
> +#objdump: -dr
> +
> +.*:     file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <.*>:
> +   0:	e01f0000 	ld1b	{za0h.b\[w12, 0\]}, p0/z, \[x0, xzr\]
> +   4:	e01f03e0 	ld1b	{za0h.b\[w12, 0\]}, p0/z, \[sp, xzr\]
> +   8:	e00003e0 	ld1b	{za0h.b\[w12, 0\]}, p0/z, \[sp, x0\]
> +   c:	e01f7e2f 	ld1b	{za0h.b\[w15, 15\]}, p7/z, \[x17, xzr\]
> +  10:	e01f7fef 	ld1b	{za0h.b\[w15, 15\]}, p7/z, \[sp, xzr\]
> +  14:	e0117fef 	ld1b	{za0h.b\[w15, 15\]}, p7/z, \[sp, x17\]
> +  18:	e05f0000 	ld1h	{za0h.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\]
> +  1c:	e05f03e0 	ld1h	{za0h.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\]

I'd like to ask whether it wouldn't have been better to suppress the
"xzr" (and, where applicable, "lsl #<n>") in disassembly. The assembler
accepts those forms, and without the extra clutter (sorry) the output
would be quite a bit easier to read imo.

Jan