[v1 3/4] RISC-V: Hypervisor Ext: Add tests

[Jan Beulich]

On 21.12.2021 03:34, Vineet Gupta wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/h-ext-32.s
> @@ -0,0 +1,64 @@
> +	hlv.b   a0, (a1)
> +	hlv.b   a0,0(a1)
> +	hlv.bu  a0, (a1)
> +	hlv.h   a1, (a2)
> +	hlv.hu  a1, (a1)
> +	hlvx.hu a1, (a2)
> +	hlv.w   a2, (a2)
> +	hlvx.wu a2, (a3)
> +	hsv.b   a0, (a1)
> +	hsv.b   a0,0(a1)
> +	hsv.h   a0, (a1)
> +	hsv.w   a0, (a1)
> +	csrr    a0, hstatus
> +	csrw    hstatus, a1
> +	csrr    a0, hedeleg
> +	csrw    hedeleg, a1
> +	csrr    a0, hideleg
> +	csrw    hideleg, a1
> +	csrr    a0, hie
> +	csrw    hie, a1
> +	csrr    a0, hcounteren
> +	csrw    hcounteren, a1
> +	csrr    a0, hgeie
> +	csrw    hgeie, a1
> +	csrr    a0, htval
> +	csrw    htval, a1
> +	csrr    a0, hip
> +	csrw    hip, a1
> +	csrr    a0, hvip
> +	csrw    hvip, a1
> +	csrr    a0, htinst
> +	csrw    htinst, a1
> +	csrr    a0, hgeip
> +	csrw    hgeip, a1

I this actually a good thing to test? Aiui this csr is r/o; I'd expect
the assembler to at least warn about write attempts ...

Jan