[v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12

[Jan Beulich]

> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1729,8 +1729,30 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"sinval.vma",      0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
>  {"sfence.w.inval",  0, INSN_CLASS_SVINVAL, "",    MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
>  {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "",    MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 },
> -{"hinval.vvma",     0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 },
> -{"hinval.gvma",     0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 },
> +
> +/* Svinval instructions + Hypervisor Ext v1.0.  */
> +{"hinval.vvma",     0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 },
> +{"hinval.gvma",     0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 },
> +{"hfence.vvma",     0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
> +{"hfence.gvma",     0, INSN_CLASS_SVINVAL_AND_H, "",    MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 },
> +{"hfence.gvma",     0, INSN_CLASS_SVINVAL_AND_H, "s",   MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 },
> +{"hfence.gvma",     0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },

I've not been able to spot pseudos with zero or one operands in the spec.
Did I miss anything? Same actually appears to apply to the pre-existing
sfence.vma ...

Jan