[PATCH 2/5] RISC-V: Cache management instructions

[Jan Beulich]

On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"sfence.vma", 0, INSN_CLASS_I,    "s,t",      MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
>  {"wfi",        0, INSN_CLASS_I,    "",         MATCH_WFI, MASK_WFI, match_opcode, 0 },
>  
> +/* Zicbom and Zicboz instructions.  */
> +{"cbo.clean",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> +{"cbo.inval",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },

Perhaps more a spec question / remark than one on the implementation:
Wouldn't it be more natural for CBO.* to have memory-like operands,
e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?

Jan