[PATCH v4 3/4] RISC-V: Fix JALR target address computation

Tsukasa OI research_trasio@irq.a4lg.com
Tue Aug 9 03:44:26 GMT 2022


Palmer Dabbelt discovered that we have wrong address computation for JALR
instruction (the initial bug is back in 2018).  This commit will fix that.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix JALR address computation.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 419c4746db9..162a2971320 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -406,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, 0, false);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
-- 
2.34.1



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