[PATCH v4 0/3] RISC-V: Add 'Zmmul' extension

Tsukasa OI research_trasio@irq.a4lg.com
Tue Aug 9 03:37:24 GMT 2022

Hi RISC-V folks,

This patch is PATCH v4 of the Zmmul support patchset primarily for Binutils
but also contains some GDB changes (simulator fix and new testcase).


Although I already assigned the copyright for my Binutils contribution, I
haven't completed the copyright assignment for my GDB contribution (because
the simulator that need to be fixed is a part of GDB).

So don't merge this until my copyright assignment completes.
Once that's done, I will send a ping to the people concerned.

To test the simulator, it requires another patch:
that fixes a minor problem on the arch-specific simulator testing.
This is also a GDB change so once my copyright assignment is done, I will ping
*and* submit the same patch to gdb-patches@sourceware.org.

Tracker on GitHub:

This is based on the ISA Manual, draft-20220707-f518c25:

This patchset also contains generic 'M' extension testcases.

[Changes: v3 -> v4]

-   Minor rebase
-   Fixed the issue that caused the failure of the simulator test.

[Changes: v2 -> v3]

-   Minor rebase
-   Fixed an issue which caused the simulator to stop working.

[Changes: v1 -> v2]

-   Minor rebase
-   On testcases, use macro symbols with no leading underscores
    (__64_bit__ -> rv64  and  __zmmul__ -> zmmul)
    Thanks to Shihua for feedback.
-   Renamed some testcases

[BUG in PATCH v2: Simulator stopped working after PATCH v2]

The cause was simple.  The simulator supports I, M and A extensions and
the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

I forgot to add INSN_CLASS_ZMMUL (for 'M') and that caused multiply
instructions to cause failure.

PATCH v3 fixed that and I added a testcase (checks whether all RV32M
instructions run without any fault).

[RFC: Implied extension (same text as PATCH v2)]

Tsukasa OI's (my) patchset implies 'Zmmul' from 'M'.
LIAO Shihua's patch does not imply 'Zmmul' from 'M'.

c.f. <https://sourceware.org/pipermail/binutils/2022-July/121685.html> (OI)
c.f. <https://sourceware.org/pipermail/binutils/2022-July/121728.html> (LIAO)

My position is derived from existing implications: Zhinx -> Zhinxmin and
Zfh -> Zfhmin.  Big problem is, those implications are implemented by ME.

I have no or a little preference here and I would like
to hear your thoughts.


Tsukasa OI (3):
  RISC-V: Add 'M' extension testcases
  RISC-V: Add 'Zmmul' extension
  RISC-V: Add 'Zmmul' failure testcases

 bfd/elfxx-riscv.c                             |  6 +++++
 gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
 gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
 .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
 .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
 gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
 gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 26 +++++++++----------
 sim/riscv/sim-main.c                          |  1 +
 sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
 20 files changed, 182 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s

base-commit: 65c9841b6fee984714509acef6e52366363072b6

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