[PATCH 0/2] RISC-V: Opcode Tidying - Operands (batch 1)

Tsukasa OI research_trasio@irq.a4lg.com
Sun Aug 7 08:00:20 GMT 2022


Hello,

This is a small patchset to clean / maintain RISC-V instruction operand types.


[PATCH 1/2]

Since `validate_riscv_insn' function lists three macro-only operand types, this
patch adds other three operands.  That means, `validate_riscv_insn' lists all
macro-only operand types with this patch.

Existing:
-   A
-   B
-   I

New in This Patch:
-   c
-   VM
-   VT

Note that `validate_riscv_insn' is called only for non-macros.  In the future,
we could reject (and make an internal error) when we encountered those macro-
only operand types on regular (non-macro) instructions.


[PATCH 2/2]

The operand type "b" has no good reasons to keep and should be removed.

-   It looks like an alias of the "s" operand type.
-   It hasn't used since the beginning.
-   Its role is not clear.

On the other hand, this patch keeps following unused operand types for now:

-   Cx     : future compressed instructions?
-   Vf, Ve : vector AMO instructions (instructions are not upstreamed
             but operand types are upstreamed already)
-   [, ]   : used by some vendors? At least, their role is clear.


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Add macro-only operands to validate_riscv_insn
  RISC-V: remove "b" operand type from disassembler

 gas/config/tc-riscv.c | 3 +++
 opcodes/riscv-dis.c   | 1 -
 2 files changed, 3 insertions(+), 1 deletion(-)


base-commit: 9663a947c09f63f75491dd4ad2f38fb448142240
-- 
2.34.1



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