[PATCH 00/12] x86: more templatization of insn templates

Jan Beulich jbeulich@suse.com
Fri Aug 5 12:17:21 GMT 2022


... reducing size of and redundancy in the source table quite a bit,
as well as the size of future patches. But first some anomalies are
being taken care of, which became obvious while trying to use the new
templates.

01: Intel: split certain AVX512-FP16 VCVT*2PH templates
02: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insns
03: fold AVX VGATHERDPD / VPGATHERDQ
04: adjust MOVSD attributes
05: adjust MOVQ to/from SReg attributes
06: revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"
07: template-ize packed/scalar vector floating point insns
08: template-ize vector packed dword/qword integer insns
09: re-order AVX512 S/G templates
10: template-ize vector packed byte/word integer insns
11: template-ize certain vector conversion insns
12: shorten certain template names

Jan


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