[PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation

Tsukasa OI research_trasio@irq.a4lg.com
Tue Aug 2 05:54:19 GMT 2022


If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing.  This commit
fixes this bug (including PR29342) by fitting an address into a 32-bit value
on RV32.

gas/ChangeLog:

	* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Clarify the role of the `wide'
	argument and rename to `is_addiw'.  Fit the address into 32-bit on
	RV32.  (print_insn_args): Reflect bool type of `is_addiw'.
---
 gas/testsuite/gas/riscv/lla32.d |  2 +-
 opcodes/riscv-dis.c             | 24 ++++++++++++++----------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index 9d875629064..8e9324c1c96 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -14,6 +14,6 @@ Disassembly of section .text:
   10:	00001537          	lui	a0,0x1
   14:	fff50513          	addi	a0,a0,-1 # fff <d>
   18:	80000537          	lui	a0,0x80000
-  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <e>
   20:	00000513          	li	a0,0
   24:	fff00513          	li	a0,-1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c6d80c3ba49..419c4746db9 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
 
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
-		     int wide)
+		     bool is_addiw)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -187,9 +187,13 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     return;
   pd->to_print_addr = true;
 
-  /* Sign-extend a 32-bit value to a 64-bit value.  */
-  if (wide)
+  /* On ADDIW, Sign-extend a 32-bit value to a 64-bit value.  */
+  if (is_addiw)
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
+
+  /* Fit into a 32-bit value on RV32.  */
+  if (xlen == 32)
+    pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
 }
 
 /* Print insn arguments for 32/64-bit code.  */
@@ -239,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'o':
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false);
 	      if (info->mach == bfd_mach_riscv64
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true);
 	      print (info->stream, dis_style_immediate, "%d",
 		     (int)EXTRACT_CITYPE_IMM (l));
 	      break;
@@ -402,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, 0, 0);
+	    maybe_print_address (pd, rs1, 0, false);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
@@ -432,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  break;
 
 	case 'o':
-	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  /* Fall through.  */
 	case 'j':
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  if (info->mach == bfd_mach_riscv64
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true);
 	  print (info->stream, dis_style_immediate, "%d",
 		 (int)EXTRACT_ITYPE_IMM (l));
 	  break;
 
 	case 'q':
-	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false);
 	  print (info->stream, dis_style_address_offset, "%d",
 		 (int)EXTRACT_STYPE_IMM (l));
 	  break;
-- 
2.34.1



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