[PATCH v2 5/5][LoongArch] LD support.
Paul Hua
paul.hua.gm@gmail.com
Thu Sep 30 09:22:00 GMT 2021
On Sat, Sep 25, 2021 at 11:06 AM 徐成华 <xuchenghua@loongson.cn> wrote:
>
>
> From 6627d27393dc67fbe63fa84e0f6bb068dd61fff6 Mon Sep 17 00:00:00 2001
> From: Chenghua Xu <xuchenghua@loongson.cn>
> Date: Sun, 19 Sep 2021 09:49:31 +0800
> Subject: [PATCH 5/5] ld: LoongArch LD Port.
>
> ---
> ld/Makefile.am | 2 +
> ld/Makefile.in | 3 +
> ld/NEWS | 4 +
> ld/configure.tgt | 4 +
> ld/emulparams/elf64loongarch-defs.sh | 39 +
> ld/emulparams/elf64loongarch.sh | 11 +
> ld/emultempl/loongarchelf.em | 87 +++
> ld/po/BLD-POTFILES.in | 1 +
> ld/testsuite/ld-loongarch-elf/disas-jirl.d | 14 +
> ld/testsuite/ld-loongarch-elf/disas-jirl.s | 5 +
> ld/testsuite/ld-loongarch-elf/jmp_op.d | 68 ++
> ld/testsuite/ld-loongarch-elf/jmp_op.s | 22 +
> .../ld-loongarch-elf/ld-loongarch-elf.exp | 34 +
> ld/testsuite/ld-loongarch-elf/macro_op.d | 732 ++++++++++++++++++
> ld/testsuite/ld-loongarch-elf/macro_op.s | 29 +
> ld/testsuite/ld-loongarch-elf/syscall-0.s | 9 +
> ld/testsuite/ld-loongarch-elf/syscall-1.s | 20 +
> ld/testsuite/ld-loongarch-elf/syscall.d | 5 +
> ld/testsuite/ld-srec/srec.exp | 6 +
> ld/testsuite/ld-unique/pr21529.d | 2 +-
> 20 files changed, 1096 insertions(+), 1 deletion(-)
> create mode 100644 ld/emulparams/elf64loongarch-defs.sh
> create mode 100644 ld/emulparams/elf64loongarch.sh
> create mode 100644 ld/emultempl/loongarchelf.em
> create mode 100644 ld/testsuite/ld-loongarch-elf/disas-jirl.d
> create mode 100644 ld/testsuite/ld-loongarch-elf/disas-jirl.s
> create mode 100644 ld/testsuite/ld-loongarch-elf/jmp_op.d
> create mode 100644 ld/testsuite/ld-loongarch-elf/jmp_op.s
> create mode 100644 ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> create mode 100644 ld/testsuite/ld-loongarch-elf/macro_op.d
> create mode 100644 ld/testsuite/ld-loongarch-elf/macro_op.s
> create mode 100644 ld/testsuite/ld-loongarch-elf/syscall-0.s
> create mode 100644 ld/testsuite/ld-loongarch-elf/syscall-1.s
> create mode 100644 ld/testsuite/ld-loongarch-elf/syscall.d
>
> diff --git a/ld/Makefile.am b/ld/Makefile.am
> index 6cfdfddc5d1..2642f0b8b5f 100644
> --- a/ld/Makefile.am
> +++ b/ld/Makefile.am
> @@ -439,6 +439,7 @@ ALL_64_EMULATION_SOURCES = \
> eelf64hppa.c \
> eelf64lppc.c \
> eelf64lppc_fbsd.c \
> + eelf64loongarch.c \
> eelf64lriscv.c \
> eelf64lriscv_lp64f.c \
> eelf64lriscv_lp64.c \
> @@ -926,6 +927,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Pc@am__quote@
> +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
> diff --git a/ld/Makefile.in b/ld/Makefile.in
> index 30fa918dfc8..7dcb19f7957 100644
> --- a/ld/Makefile.in
> +++ b/ld/Makefile.in
> @@ -928,6 +928,7 @@ ALL_64_EMULATION_SOURCES = \
> eelf64hppa.c \
> eelf64lppc.c \
> eelf64lppc_fbsd.c \
> + eelf64loongarch.c \
> eelf64lriscv.c \
> eelf64lriscv_lp64f.c \
> eelf64lriscv_lp64.c \
> @@ -1426,6 +1427,7 @@ distclean-compile:
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
> +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Po@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Po@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@
> @@ -2590,6 +2592,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Pc@am__quote@
> +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
> @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
> diff --git a/ld/NEWS b/ld/NEWS
> index 6e0b56658d3..df993d7bb2a 100644
> --- a/ld/NEWS
> +++ b/ld/NEWS
> @@ -1,5 +1,9 @@
> -*- text -*-
>
> +Changes in 2.37:
> +
> +* Add support for the LoongArch instruction set.
> +
> * Add -z indirect-extern-access/-z noindirect-extern-access to x86 ELF
> linker to control canonical function pointers and copy relocation.
>
> diff --git a/ld/configure.tgt b/ld/configure.tgt
> index 5411104ec36..9a491eb3df3 100644
> --- a/ld/configure.tgt
> +++ b/ld/configure.tgt
> @@ -1036,6 +1036,10 @@ z8k-*-coff) targ_emul=z8002
> targ_extra_emuls=z8001
> targ_extra_ofiles=
> ;;
> +loongarch32-*) targ_emul=elf32loongarch
> + ;;
> +loongarch64-*) targ_emul=elf64loongarch
> + ;;
> *-*-ieee*) targ_emul=vanilla
> targ_extra_ofiles=
> ;;
> diff --git a/ld/emulparams/elf64loongarch-defs.sh b/ld/emulparams/elf64loongarch-defs.sh
> new file mode 100644
> index 00000000000..c793f5d8388
> --- /dev/null
> +++ b/ld/emulparams/elf64loongarch-defs.sh
> @@ -0,0 +1,39 @@
> +# This is an ELF platform.
> +SCRIPT_NAME=elf
> +ARCH=loongarch
> +NO_REL_RELOCS=yes
> +
> +TEMPLATE_NAME=elf
> +EXTRA_EM_FILE=loongarchelf
> +
> +ELFSIZE=64
> +
> +if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then
> + case " $EMULATION_LIBPATH " in
> + *" ${EMULATION_NAME} "*)
> + NATIVE=yes
> + ;;
> + esac
> +fi
> +
> +# Enable shared library support for everything except an embedded elf target.
> +case "$target" in
> + loongarch*-elf)
> + ;;
> + *)
> + GENERATE_SHLIB_SCRIPT=yes
> + GENERATE_PIE_SCRIPT=yes
> + ;;
> +esac
> +
> +# In all cases, the number is big-endian.
> +# LoongArch nop is 'andi $r0,$r0,0'.
> +NOP=0x00004003
> +
> +TEXT_START_ADDR=0x120000000
> +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
> +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
> +
> +SEPARATE_GOTPLT=0
> +INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
> +INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
> diff --git a/ld/emulparams/elf64loongarch.sh b/ld/emulparams/elf64loongarch.sh
> new file mode 100644
> index 00000000000..d7b2229e213
> --- /dev/null
> +++ b/ld/emulparams/elf64loongarch.sh
> @@ -0,0 +1,11 @@
> +source_sh ${srcdir}/emulparams/elf64loongarch-defs.sh
> +OUTPUT_FORMAT="elf64-loongarch"
> +
> +case "$target" in
> + loongarch64*-linux*)
> + case "$EMULATION_NAME" in
> + *64*)
> + LIBPATH_SUFFIX="64";;
> + esac
> + ;;
> +esac
> diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
> new file mode 100644
> index 00000000000..b688ef7bc1d
> --- /dev/null
> +++ b/ld/emultempl/loongarchelf.em
> @@ -0,0 +1,87 @@
> +# This shell script emits a C file. -*- C -*-
> +# Copyright (C) 2021 Free Software Foundation, Inc.
> +# Contributed by Loongson Ltd.
> +#
> +# This file is part of the GNU Binutils.
> +#
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# the Free Software Foundation; either version 3 of the License, or
> +# (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; see the file COPYING3. If not,
> +# see <http: www.gnu.org="" licenses=""></http:>.
> +
> +fragment <<eof +="" +#include="" "ldmain.h"="" "ldctor.h"="" "elf="" loongarch.h"="" +static="" void="" +larch_elf_before_allocation="" (void)="" +{="" gld${emulation_name}_before_allocation="" ();="" if="" (link_info.discard="=" discard_sec_merge)="" link_info.discard="discard_l;" (!bfd_link_relocatable="" (&link_info))="" {="" *="" we="" always="" need="" at="" least="" some="" relaxation="" to="" handle="" code="" alignment.="" (relaxation_disabled_by_user)="" target_enable_relaxation;="" else="" enable_relaxation;="" }="" link_info.relax_pass="3;" +}="" +gld${emulation_name}_after_allocation="" int="" need_layout="0;" don't="" attempt="" discard="" unused="" .eh_frame="" sections="" until="" the="" final="" link,="" as="" can't="" reliably="" tell="" they're="" used="" after="" relaxation.="" (link_info.output_bfd,="" &link_info);="" (need_layout="" <="" 0)="" einfo="" (_("%x%p:="" .stab="" edit:="" %e\n"));="" return;="" gld${emulation_name}_map_segments="" (need_layout);="" ldelf_map_segments="" this="" is="" a="" convenient="" point="" bfd="" about="" target="" specific="" flags.="" output="" has="" been="" created,="" but="" before="" inputs="" are="" read.="" +larch_create_output_section_statements="" see="" pr="" 22920="" for="" an="" example="" of="" why="" necessary.="" (strstr="" (bfd_get_target="" (link_info.output_bfd),="" "loong")="=" null)="" (_("%f%p:="" error:="" cannot="" change="" format"="" "="" whilst="" linking="" %s="" binaries\n"),="" "loongarch");="" +eof="" +ldemul_before_allocation="larch_elf_before_allocation" +ldemul_after_allocation="gld${EMULATION_NAME}_after_allocation" +ldemul_create_output_section_statements="larch_create_output_section_statements" diff="" --git="" ld="" po="" bld-potfiles.in="" b="" index="" 54975cd10c3..ddbaa0dcb9b="" 100644="" ---="" +++="" @@="" -184,6="" +184,7="" eelf64briscv_lp64f.c="" eelf64btsmip.c="" eelf64btsmip_fbsd.c="" eelf64hppa.c="" +eelf64loongarch.c="" eelf64lppc.c="" eelf64lppc_fbsd.c="" eelf64lriscv.c="" testsuite="" ld-loongarch-elf="" disas-jirl.d="" new="" file="" mode="" 00000000000..8c60f634156="" dev="" null="" -0,0="" +1,14="" +#name:="" jirl="" zero-offset="" symbols="" +#source:="" disas-jirl.s="" +#ld:="" --no-relax="" +#objdump:="" -d="" +.*:[="" ]+file="" format="" .*="" +disassembly="" section="" .text:="" +0000000120000078="" <_start="">:
> +[ ]+120000078:[ ]+1c000014 [ ]+pcaddu12i[ ]+[ ]+\$t8, 0
> +[ ]+12000007c:[ ]+02c00294 [ ]+addi.d[ ]+[ ]+\$t8, \$t8, 0
> +[ ]+120000080:[ ]+4c000281 [ ]+jirl[ ]+[ ]+\$ra, \$t8, 0
> diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.s b/ld/testsuite/ld-loongarch-elf/disas-jirl.s
> new file mode 100644
> index 00000000000..d6027c9cc9a
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.s
> @@ -0,0 +1,5 @@
> + .text
> + .globl _start
> +_start:
> + la.local $r20,_start
> + jirl $r1, $r20, 0
> diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
> new file mode 100644
> index 00000000000..e6c50e8e991
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
> @@ -0,0 +1,68 @@
> +#as:
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0000000000000000 <.text>:
> +[ ]+0:[ ]+03400000 [ ]+andi[ ]+[ ]+\$zero, \$zero, 0x0
> +[ ]+4:[ ]+60000004 [ ]+bgtz[ ]+[ ]+\$a0, 0[ ]+# 0x4
> +[ ]+[ ]+[ ]+4: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+4: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+8:[ ]+64000080 [ ]+bgez[ ]+[ ]+\$a0, 0[ ]+# 0x8
> +[ ]+[ ]+[ ]+8: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+8: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+c:[ ]+64000004 [ ]+blez[ ]+[ ]+\$a0, 0[ ]+# 0xc
> +[ ]+[ ]+[ ]+c: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+c: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+10:[ ]+40000080 [ ]+beqz[ ]+[ ]+\$a0, 0[ ]+# 0x10
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ ]+\*ABS\*
> +[ ]+14:[ ]+44000080 [ ]+bnez[ ]+[ ]+\$a0, 0[ ]+# 0x14
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ ]+\*ABS\*
> +[ ]+18:[ ]+48000000 [ ]+bceqz[ ]+[ ]+\$fcc0, 0[ ]+# 0x18
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ ]+\*ABS\*
> +[ ]+1c:[ ]+48000100 [ ]+bcnez[ ]+[ ]+\$fcc0, 0[ ]+# 0x1c
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ ]+\*ABS\*
> +[ ]+20:[ ]+4c000080 [ ]+jirl[ ]+[ ]+\$zero, \$a0, 0
> +[ ]+24:[ ]+50000000 [ ]+b[ ]+[ ]+0[ ]+# 0x24
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_POP_32_S_0_10_10_16_S2[ ]+\*ABS\*
> +[ ]+28:[ ]+54000000 [ ]+bl[ ]+[ ]+0[ ]+# 0x28
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_POP_32_S_0_10_10_16_S2[ ]+\*ABS\*
> +[ ]+2c:[ ]+58000085 [ ]+beq[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x2c
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+30:[ ]+5c000085 [ ]+bne[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x30
> +[ ]+[ ]+[ ]+30: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+30: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+34:[ ]+60000085 [ ]+blt[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x34
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+38:[ ]+600000a4 [ ]+blt[ ]+[ ]+\$a1, \$a0, 0[ ]+# 0x38
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+3c:[ ]+64000085 [ ]+bge[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x3c
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+40:[ ]+640000a4 [ ]+bge[ ]+[ ]+\$a1, \$a0, 0[ ]+# 0x40
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+44:[ ]+68000085 [ ]+bltu[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x44
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+48:[ ]+680000a4 [ ]+bltu[ ]+[ ]+\$a1, \$a0, 0[ ]+# 0x48
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+4c:[ ]+6c000085 [ ]+bgeu[ ]+[ ]+\$a0, \$a1, 0[ ]+# 0x4c
> +[ ]+[ ]+[ ]+4c: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+4c: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> +[ ]+50:[ ]+6c0000a4 [ ]+bgeu[ ]+[ ]+\$a1, \$a0, 0[ ]+# 0x50
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_PUSH_PCREL[ ]+L1
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_POP_32_S_10_16_S2[ ]+\*ABS\*
> diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loongarch-elf/jmp_op.s
> new file mode 100644
> index 00000000000..01b043d19eb
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.s
> @@ -0,0 +1,22 @@
> +.L1:
> + nop
> + bgtz $r4,L1
> + bgez $r4,L1
> + blez $r4,L1
> + beqz $r4,L1
> + bnez $r4,L1
> + bceqz $fcc0,L1
> + bcnez $fcc0,L1
> + jr $r4
> + b L1
> + bl L1
> + beq $r4,$r5,L1
> + bne $r4,$r5,L1
> + blt $r4,$r5,L1
> + bgt $r4,$r5,L1
> + bge $r4,$r5,L1
> + ble $r4,$r5,L1
> + bltu $r4,$r5,L1
> + bgtu $r4,$r5,L1
> + bgeu $r4,$r5,L1
> + bleu $r4,$r5,L1
> diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> new file mode 100644
> index 00000000000..0d31c2a6741
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> @@ -0,0 +1,34 @@
> +# Expect script for LoongArch ELF linker tests
> +# Copyright (C) 2021 Free Software Foundation, Inc.
> +#
> +# This file is part of the GNU Binutils.
> +#
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# the Free Software Foundation; either version 3 of the License, or
> +# (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
> +# MA 02110-1301, USA.
> +#
> +
> +proc loongarch_choose_lp64_emul {} {
> + if { [istarget "loongarch64be-*"] } {
> + return "elf64bloongarch"
> + }
> + return "elf64lloongarch"
> +}
> +
> +if [istarget "loongarch*-*-*"] {
> + run_dump_test "jmp_op"
> + run_dump_test "macro_op"
> + run_dump_test "syscall"
> + run_dump_test "disas-jirl"
> +}
> diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
> new file mode 100644
> index 00000000000..548553eedbc
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
> @@ -0,0 +1,732 @@
> +#as:
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0000000000000000 <.text>:
> +[ ]+0:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
> +[ ]+4:[ ]+02bffc04 [ ]+addi.w[ ]+[ ]+\$a0, \$zero, -1\(0xfff\)
> +[ ]+8:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
> +[ ]+c:[ ]+02bffc04 [ ]+addi.w[ ]+[ ]+\$a0, \$zero, -1\(0xfff\)
> +[ ]+10:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+10: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+14:[ ]+28c00084 [ ]+ld.d[ ]+[ ]+\$a0, \$a0, 0
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+18:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+18: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+1c:[ ]+28c00084 [ ]+ld.d[ ]+[ ]+\$a0, \$a0, 0
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+1c: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+20:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000000
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+20: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+24:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000004
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_AND[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+24: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
> +[ ]+28:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000008
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+28: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+2c:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+2c: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+30:[ ]+380c1484 [ ]+ldx.d[ ]+[ ]+\$a0, \$a0, \$a1
> +[ ]+34:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+34: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+38:[ ]+28c00084 [ ]+ld.d[ ]+[ ]+\$a0, \$a0, 0
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+38: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+3c:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000000
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+3c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+40:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000004
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_AND[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+40: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
> +[ ]+44:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000008
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+44: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+48:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+48: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+4c:[ ]+380c1484 [ ]+ldx.d[ ]+[ ]+\$a0, \$a0, \$a1
> +[ ]+50:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+50: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+54:[ ]+28c00084 [ ]+ld.d[ ]+[ ]+\$a0, \$a0, 0
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+54: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+58:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000000
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+58: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+5c:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000004
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_AND[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+5c: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
> +[ ]+60:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
> +[ ]+[ ]+[ ]+60: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000008
> +[ ]+[ ]+[ ]+60: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+60: R_LARCH_SOP_ADD[ ]+\*ABS\*
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> +[ ]+[ ]+[ ]+d0: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
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> +[ ]+d8:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
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> +[ ]+[ ]+[ ]+d8: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+d8: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+d8: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+d8: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+d8: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
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> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_PUSH_GPREL[ ]+L1
> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+dc: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
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> +[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
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> +[ ]+[ ]+[ ]+134: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
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> +[ ]+13c:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
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> +[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+13c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+13c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+13c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+140:[ ]+02c00084 [ ]+addi.d[ ]+[ ]+\$a0, \$a0, 0
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+140: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+144:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000000
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+144: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+148:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000004
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_SUB[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_AND[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+148: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
> +[ ]+14c:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x80000008
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_SL[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+14c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
> +[ ]+150:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_ADD[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_SR[ ]+\*ABS\*
> +[ ]+[ ]+[ ]+150: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
> +[ ]+154:[ ]+00109484 [ ]+add.d[ ]+[ ]+\$a0, \$a0, \$a1
> diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.s b/ld/testsuite/ld-loongarch-elf/macro_op.s
> new file mode 100644
> index 00000000000..c15e364d4d0
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/macro_op.s
> @@ -0,0 +1,29 @@
> +.L1:
> + li.w $r4,0
> + li.w $r4,0xffffffff
> + li.d $r4,0
> + li.d $r4,0xffffffffffffffff
> + la $r4,L1
> + la.global $r4,L1
> + la.global $r4,$r5,L1
> + la.global $r4,L1
> + la.global $r4,$r5,L1
> + la.global $r4,L1
> + la.global $r4,$r5,L1
> + la.local $r4,L1
> + la.local $r4,$r5,L1
> + la.local $r4,L1
> + la.local $r4,$r5,L1
> + la.abs $r4,L1
> + la.pcrel $r4,L1
> + la.pcrel $r4,L1
> + la.pcrel $r4,$r5,L1
> + la.got $r4,L1
> + la.got $r4,$r5,L1
> + la.tls.le $r4,L1
> + la.tls.ie $r4,L1
> + la.tls.ie $r4,$r5,L1
> + la.tls.ld $r4,L1
> + la.tls.ld $r4,$r5,L1
> + la.tls.gd $r4,L1
> + la.tls.gd $r4,$r5,L1
> diff --git a/ld/testsuite/ld-loongarch-elf/syscall-0.s b/ld/testsuite/ld-loongarch-elf/syscall-0.s
> new file mode 100644
> index 00000000000..f31e05f364c
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/syscall-0.s
> @@ -0,0 +1,9 @@
> +.globl _start
> +
> +.section .text.hot
> +_start:
> + la.global $r20,cc
> + jirl $r1, $r20, 0
> + addi.w $r11,$r0,93
> + addi.w $r4,$r0,0
> + syscall 0
> diff --git a/ld/testsuite/ld-loongarch-elf/syscall-1.s b/ld/testsuite/ld-loongarch-elf/syscall-1.s
> new file mode 100644
> index 00000000000..e9acee9e303
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/syscall-1.s
> @@ -0,0 +1,20 @@
> +.globl cc
> +
> +.text
> +cc:
> + addi.d $r3,$r3,-16
> + st.d $r1,$r3,8
> + la.local $r5,.LC0
> + addi.w $r4,$r0,0
> + addi.w $r6, $r0,12
> + addi.w $r11, $r0, 64
> + syscall 0
> + ld.d $r1,$r3,8
> + addi.d $r3,$r3,16
> + jirl $r0, $r1, 0
> +.LC0:
> + .ascii "hello world\012\000"
> + .text
> + .align 2
> + .globl world
> + .type world, @function
> diff --git a/ld/testsuite/ld-loongarch-elf/syscall.d b/ld/testsuite/ld-loongarch-elf/syscall.d
> new file mode 100644
> index 00000000000..b599277f522
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/syscall.d
> @@ -0,0 +1,5 @@
> +#name: syscall
> +#source: syscall-0.s
> +#source: syscall-1.s
> +#objdump: -d
> +#pass
> diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp
> index 57380ca3146..30a5a3da912 100644
> --- a/ld/testsuite/ld-srec/srec.exp
> +++ b/ld/testsuite/ld-srec/srec.exp
> @@ -291,6 +291,12 @@ proc run_srec_test { test objs } {
> setup_xfail "riscv*-*-*"
> }
>
> + # LoongArch targets cannot convert format in the linker
> + # using the --oformat command line switch
> + if [istarget loongarch*-*-*] {
> + setup_xfail "loongarch*-*-*"
> + }
> +
> # V850 targets need libgcc.a
> if [istarget v850*-*-elf] {
> set objs "$objs -L ../gcc -lgcc"
> diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d
> index fb637943909..896f8722782 100644
> --- a/ld/testsuite/ld-unique/pr21529.d
> +++ b/ld/testsuite/ld-unique/pr21529.d
> @@ -1,6 +1,6 @@
> #ld: --oformat binary -T pr21529.ld -e main
> #objdump: -s -b binary
> -#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-*
> +#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* loongarch*-*-*
> # Skip targets which can't change output format to binary.
>
> #pass
> --
> 2.27.0
>
>
>
> </eof></xuchenghua@loongson.cn>
>
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