[integration 0/1] RISC-V: Add CSRs and opcodes of T-HEAD XUANTIE CPUs

[Nelson Chu]

On Tue, Sep 7, 2021 at 5:20 PM Lifang Xia <lifang_xia@c-sky.com> wrote:
>
>
> Hi Nelson,
> Thanks for reveiwing these patches.
> That's my fault that I'm not checking these patches in
> binutils-integration-branch. I thought there are not much changes from
> master. Sorry. :(

That' fine :)

> I re-write the patches, merge them to one patch here.

The v2 version looks pretty good to me, thanks!  Committed.

> The extended solutions is suitable for adding CSRs and opcodes of T-HEAD
> XUANTIE CPUs.
> As you metioned in the previous e-mail, I agree with that it is not a
> good solution for vendors. Is there any discussions about that?

Not yet, but we can discuss and update them in the future.  Currently
your patch is good enough, so I already committed it, with some minor
updates.  Most of the updates are related to GNU coding standards.
Besides, I renamed ISA_SPEC_CLASS_VENDOR_THEAD to
VENDOR_SPEC_CLASS_THEAD, since I suppose vendor extensions should be
controlled by vendor specs, rather than the isa spec.

However, we are considering moving the stable vendor stuff back to the
mainline, based on the extended structures.  So before that, the
t-head and vendor extension will be maintained at the integration
branch for now.

Thanks
Nelson