[integration v2 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0

[Nelson Chu]

Committed these patches into riscv integration branch.  I am going to
move the whole rvv 1.0 extensions back to the master branch, since rvv
1.0 was frozen and at the public review stage.

Thanks
Nelson

On Tue, Oct 5, 2021 at 8:51 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Hi Guys,
>
> There are four patches used to update the rvv from v1.0 to 1.0,
> * [integration v2 1/4] RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.
> * [integration v2 2/4] RISC-V/rvv: Update constraints for widening and narrowing instructions.
> * [integration v2 3/4] RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.
> * [integration v2 4/4] RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.
>
> I still send the rvv patches to integration branch, since it should be
> easier to review.  After the reviewing, I will merge the whole rvv patches
> into the one, and then move it from the integration branch to mainline,
> since the rvv v1.0 is frozen and at the public review stage for now.
>
> Thanks
> Nelson
>
>