[PATCH 6/7] opcodes: LoongArch: make beq/bne's operand order "rd, rj" to be consistent with all others

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

This has no functional impact, but keeps the instruction format nice and
clean; all register operands are ordered LSB-first.

2021-10-25  WANG Xuerui <git@xen0n.name>

opcodes/
        * loongarch-opc.c: Swap operand order of beq and bne.
---
 opcodes/loongarch-opc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 687bfd776c5..277ef60c193 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -748,9 +748,9 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
   { 0x0,	0x0,		"bl",		"la",				"bl %%pcrel(%1)",		0, 0, 0 },
   { 0x54000000, 0xfc000000,	"bl",		"sb0:10|10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"beq",		"r,r,la",			"beq %1,%2,%%pcrel(%3)",	0, 0, 0 },
-  { 0x58000000, 0xfc000000,	"beq",		"r5:5,r0:5,sb10:16<<2",		0,				0, 0, 0 },
+  { 0x58000000, 0xfc000000,	"beq",		"r0:5,r5:5,sb10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"bne",		"r,r,la",			"bne %1,%2,%%pcrel(%3)",	0, 0, 0 },
-  { 0x5c000000, 0xfc000000,	"bne",		"r5:5,r0:5,sb10:16<<2",		0,				0, 0, 0 },
+  { 0x5c000000, 0xfc000000,	"bne",		"r0:5,r5:5,sb10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"bgt",		"r,r,la",			"bgt %1,%2,%%pcrel(%3)",	0, 0, 0 },
   { 0x60000000, 0xfc000000,	"bgt",		"r0:5,r5:5,sb10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"ble",		"r,r,la",			"ble %1,%2,%%pcrel(%3)",	0, 0, 0 },
-- 
2.33.1