[PATCH 5/6] aarch64: Make LOR registers conditional on +lor
Richard Sandiford
richard.sandiford@arm.com
Tue Nov 30 12:23:32 GMT 2021
We have a +lor feature flag for the Limited Ordering Regions
extension, but the associated registers didn't use it.
Tested on aarch64-linux-gnu. OK to install?
Richard
opcodes/
* aarch64-opc.c (SR_LOR): New macro.
(aarch64_sys_regs): Use it for lorc_el1, lorea_el1, lorn_el1 and
lorsa_el1.
gas/
* testsuite/gas/aarch64/sysreg-7.s: Enable +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.s: Test for LOR registers
without +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.d: Update accordingly.
* testsuite/gas/aarch64/illegal-sysreg-7.l: Likewise.
---
gas/testsuite/gas/aarch64/illegal-sysreg-7.d | 2 +-
gas/testsuite/gas/aarch64/illegal-sysreg-7.l | 4 ++++
gas/testsuite/gas/aarch64/illegal-sysreg-7.s | 6 ++++++
gas/testsuite/gas/aarch64/sysreg-7.s | 2 ++
opcodes/aarch64-opc.c | 10 ++++++----
5 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.d b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
index d7a11ed3720..98bc9a04835 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
@@ -1,2 +1,2 @@
#source: illegal-sysreg-7.s
-#warning_output: illegal-sysreg-7.l
+#error_output: illegal-sysreg-7.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.l b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
index 1db54b34530..697b7064112 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
@@ -1,2 +1,6 @@
.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'lorc_el1'
+.*: Error: selected processor does not support system register name 'lorea_el1'
+.*: Error: selected processor does not support system register name 'lorn_el1'
+.*: Error: selected processor does not support system register name 'lorsa_el1'
.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_vtr_el2,x0'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.s b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
index 311e18227b2..31094538b87 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
@@ -1,2 +1,8 @@
+/* Missing +lor. */
+mrs x0, lorc_el1
+mrs x0, lorea_el1
+mrs x0, lorn_el1
+mrs x0, lorsa_el1
+
/* Write to R/O system registers. */
msr ich_vtr_el2, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg-7.s
index 3d438d1c74a..94dd85b1a03 100644
--- a/gas/testsuite/gas/aarch64/sysreg-7.s
+++ b/gas/testsuite/gas/aarch64/sysreg-7.s
@@ -1,3 +1,5 @@
+.arch armv8-a+lor
+
/* Read from system registers. */
mrs x0, lorc_el1
mrs x0, lorea_el1
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ace7032b7fb..a0959155787 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3990,6 +3990,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3)
#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
+#define SR_LOR(n,e,f) SR_FEAT (n,e,f,LOR)
#define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN)
#define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS)
#define SR_SME(n,e,f) SR_FEAT (n,e,f,SME)
@@ -4714,10 +4715,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0),
SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ),
- SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0),
- SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0),
- SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0),
- SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0),
+ SR_LOR ("lorc_el1", CPENC (3,0,C10,C4,3), 0),
+ SR_LOR ("lorea_el1", CPENC (3,0,C10,C4,1), 0),
+ SR_LOR ("lorn_el1", CPENC (3,0,C10,C4,2), 0),
+ SR_LOR ("lorsa_el1", CPENC (3,0,C10,C4,0), 0),
+
SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0),
SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0),
SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0),
--
2.25.1
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