[PATCH v2 2/3] RISC-V: Add instructions and operand set for z[fdq]inx

[Palmer Dabbelt]

On Wed, 17 Nov 2021 04:10:07 PST (-0800), jiawei@iscas.ac.cn wrote:
> Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
> verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Added support for
>   z*inx extension.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
>
> include/ChangeLog:
>
> * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
>   z*inx.
> * riscv-opc.c: Reused INSN_CLASS_* for z*inx.
>
> ---
>  bfd/elfxx-riscv.c      |   9 ++
>  gas/config/tc-riscv.c  |   4 +-
>  include/opcode/riscv.h |   3 +
>  opcodes/riscv-dis.c    |   4 +
>  opcodes/riscv-opc.c    | 296 ++++++++++++++++++++---------------------
>  5 files changed, 167 insertions(+), 149 deletions(-)

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>