[PATCH v2 0/3] RISC-V: Zfinx extension support

[jiawei]

This patch is support zfinx extension on binutils, 
zfinx is not compatible with any float extension 
and use gpr replace fpr. We adjust the opreand set
when zfinx used. 

For disassemble part, use the function "riscv_subset_supports" 
to check if zfinx is enable as Nelson Chu's comment, 
once the arch has zfinx, then the disassblemer will 
use gpr instead of fpr with instruction generator.

Version log:

v2: Remove zfinx elf flag, use riscv_subset_supports to recongenize
whether zfinx enable or not. Adjust INSN_CLASS_* implement order in
patches. Use INSN_CLASS_F_OR_ZFINX instead of INSN_CLASS_ZFINX and
add register group choice in reg_lookup. Add Changelog in all patches
Thanks for Nelson Chu's comment.

jiawei (3):
  RISC-V: Add mininal support for z[fdq]inx
  RISC-V: Add instructions and operand set for z[fdq]inx
  RISC-V: Add testcases  for z[fdq]inx

 bfd/elfxx-riscv.c               |  21 +++
 gas/config/tc-riscv.c           |   4 +-
 gas/testsuite/gas/riscv/zdinx.d |  42 +++++
 gas/testsuite/gas/riscv/zdinx.s |  34 ++++
 gas/testsuite/gas/riscv/zfinx.d |  40 +++++
 gas/testsuite/gas/riscv/zfinx.s |  32 ++++
 gas/testsuite/gas/riscv/zqinx.d |  44 +++++
 gas/testsuite/gas/riscv/zqinx.s |  36 ++++
 include/opcode/riscv.h          |   3 +
 opcodes/riscv-dis.c             |   4 +
 opcodes/riscv-opc.c             | 296 ++++++++++++++++----------------
 11 files changed, 407 insertions(+), 149 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zdinx.d
 create mode 100644 gas/testsuite/gas/riscv/zdinx.s
 create mode 100644 gas/testsuite/gas/riscv/zfinx.d
 create mode 100644 gas/testsuite/gas/riscv/zfinx.s
 create mode 100644 gas/testsuite/gas/riscv/zqinx.d
 create mode 100644 gas/testsuite/gas/riscv/zqinx.s

-- 
2.25.1