[PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
陈嘉炜
jiawei@iscas.ac.cn
Thu Nov 11 03:30:38 GMT 2021
> -----原始邮件-----
> 发件人: "Nelson Chu" <nelson.chu@sifive.com>
> 发送时间: 2021-11-10 17:26:38 (星期三)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: Binutils <binutils@sourceware.org>, "Kito Cheng" <kito.cheng@sifive.com>, "Jim Wilson" <jimw@sifive.com>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, "Palmer Dabbelt" <palmer@dabbelt.com>, "Andrew Waterman" <andrew@sifive.com>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, siyu@isrc.iscas.ac.cn, "Andreas Schwab" <schwab@linux-m68k.org>, "Jan Beulich" <jbeulich@suse.com>
> 主题: Re: [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
>
> On Thu, Nov 4, 2021 at 1:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support.
> >
> > The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64.
> >
> > Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions.
> >
> > Add new Entropy Source CSR define 'seed' located at address 0x015.
> > ---
> > gas/config/tc-riscv.c | 24 +++++++++++
> > include/opcode/riscv-opc.h | 75 ++++++++++++++++++++++++++++++++
> > include/opcode/riscv.h | 7 +++
> > opcodes/riscv-dis.c | 8 ++++
> > opcodes/riscv-opc.c | 87 ++++++++++++++++++++++++++++++--------
> > 5 files changed, 184 insertions(+), 17 deletions(-)
> >
> > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> > index 5e7009b5696..2812432b8d6 100644
> > --- a/gas/config/tc-riscv.c
> > +++ b/gas/config/tc-riscv.c
> > @@ -1183,6 +1183,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> > case 'I': break; /* Macro operand, must be constant. */
> > case 'D': /* RD, floating point. */
> > case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
> > + case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
> > + case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
> > case 'Z': /* RS1, CSR number. */
> > case 'S': /* RS1, floating point. */
> > case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> > @@ -2804,6 +2806,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> > }
> > break;
> >
> > + case 'y': /* bs immediate */
> > + my_getExpression (imm_expr, asarg);
> > + check_absolute_expr (ip, imm_expr, FALSE);
> > + if ((unsigned long)imm_expr->X_add_number > 3)
> > + as_bad(_("Improper bs immediate (%lu)"),
> > + (unsigned long)imm_expr->X_add_number);
> > + INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
> > + imm_expr->X_op = O_absent;
> > + asarg = expr_end;
> > + continue;
> > +
> > + case 'Y': /* rcon immediate */
>
> rnum, is this a typo?
Sorry for the error typo, I had fix it.
> > + my_getExpression (imm_expr, asarg);
> > + check_absolute_expr (ip, imm_expr, FALSE);
> > + if ((unsigned long)imm_expr->X_add_number > 10)
> > + as_bad(_("Improper rnum immediate (%lu)"),
> > + (unsigned long)imm_expr->X_add_number);
> > + INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
> > + imm_expr->X_op = O_absent;
> > + asarg = expr_end;
> > + continue;
> > +
> > case 'z':
> > if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
> > || imm_expr->X_op != O_constant
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 45a207da0cd..16a7cf243a9 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -443,6 +443,8 @@
> > #define MASK_SEXT_H 0xfff0707f
> > #define MATCH_PACK 0x8004033
> > #define MASK_PACK 0xfe00707f
> > +#define MATCH_PACKH 0x8007033
> > +#define MASK_PACKH 0xfe00707f
> > #define MATCH_PACKW 0x800403b
> > #define MASK_PACKW 0xfe00707f
> > #define MATCH_ANDN 0x40007033
> > @@ -461,6 +463,10 @@
> > #define MASK_GREVI 0xfc00707f
> > #define MATCH_GORCI 0x28005013
> > #define MASK_GORCI 0xfc00707f
> > +#define MATCH_SHFLI 0x8001013
> > +#define MASK_SHFLI 0xfc00707f
>
> Consider current bitmanip spec,
> https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/insns/zip.adoc
>
> The encoding should be,
> 31-25, 24-20, 19-15, 14-12, 11-7, 6-2, 1-0
> 0x4, 0x1e, rs1, 0x1, rd, 0x4, 0x3
> 0000100, 11110, rs1, 001, rd, 00100, 11
> 1111111, 11111, rs1(00000), 111, rd(00000), 11111, 11, so the MASK_ZIP
> should be 0xfff0707f.
>
> But in the past, we usually use shfli/unshfli to encode the zip/unzip,
> so consider the old spec,
> https://github.com/riscv/riscv-bitmanip/blob/main-history/bitmanip-draft.pdf
>
> 31-26, 25-20, 19-15, 14-12, 11-7, 6-2, 1-0
> 000010, imm, rs1, 0x1, rd, 0x4, 0x3
> 1111111, imm, rs1, 001, rd, 00100, 11
> 1111111, imm(000000), rs1(00000), 111, rd(00000), 11111, 11, so the
> MASK_SHFLI should be 0xfe00707f, rather than 0xfc00707f.
>
> > +#define MATCH_UNSHFLI 0x8005013
> > +#define MASK_UNSHFLI 0xfc00707f
>
> Likewise, the MASK_UNSHFLI should be 0xfe00707f.
>
Thank you for the mention, it will be fixed in next version.
> > #define MATCH_CLZW 0x6000101b
> > #define MASK_CLZW 0xfff0707f
> > #define MATCH_CTZW 0x6010101b
> > @@ -495,6 +501,10 @@
> > #define MASK_CLMULH 0xfe00707f
> > #define MATCH_CLMULR 0xa002033
> > #define MASK_CLMULR 0xfe00707f
> > +#define MATCH_XPERM4 0x28002033
> > +#define MASK_XPERM4 0xfe00707f
> > +#define MATCH_XPERM8 0x28004033
> > +#define MASK_XPERM8 0xfe00707f
> > #define MATCH_BCLRI 0x48001013
> > #define MASK_BCLRI 0xfc00707f
> > #define MATCH_BSETI 0x28001013
> > @@ -637,6 +647,64 @@
> > #define MASK_C_LDSP 0xe003
> > #define MATCH_C_SDSP 0xe002
> > #define MASK_C_SDSP 0xe003
> > +#define MATCH_SM3P0 0x10801013
> > +#define MASK_SM3P0 0xfff0707f
> > +#define MATCH_SM3P1 0x10901013
> > +#define MASK_SM3P1 0xfff0707f
> > +#define MATCH_SHA256SUM0 0x10001013
> > +#define MASK_SHA256SUM0 0xfff0707f
> > +#define MATCH_SHA256SUM1 0x10101013
> > +#define MASK_SHA256SUM1 0xfff0707f
> > +#define MATCH_SHA256SIG0 0x10201013
> > +#define MASK_SHA256SIG0 0xfff0707f
> > +#define MATCH_SHA256SIG1 0x10301013
> > +#define MASK_SHA256SIG1 0xfff0707f
> > +#define MATCH_SHA512SUM0R 0x50000033
> > +#define MASK_SHA512SUM0R 0xfe00707f
> > +#define MATCH_SHA512SUM1R 0x52000033
> > +#define MASK_SHA512SUM1R 0xfe00707f
> > +#define MATCH_SHA512SIG0L 0x54000033
> > +#define MASK_SHA512SIG0L 0xfe00707f
> > +#define MATCH_SHA512SIG0H 0x5c000033
> > +#define MASK_SHA512SIG0H 0xfe00707f
> > +#define MATCH_SHA512SIG1L 0x56000033
> > +#define MASK_SHA512SIG1L 0xfe00707f
> > +#define MATCH_SHA512SIG1H 0x5e000033
> > +#define MASK_SHA512SIG1H 0xfe00707f
> > +#define MATCH_SM4ED 0x30000033
> > +#define MASK_SM4ED 0x3e00707f
> > +#define MATCH_SM4KS 0x34000033
> > +#define MASK_SM4KS 0x3e00707f
> > +#define MATCH_AES32ESMI 0x26000033
> > +#define MASK_AES32ESMI 0x3e00707f
> > +#define MATCH_AES32ESI 0x22000033
> > +#define MASK_AES32ESI 0x3e00707f
> > +#define MATCH_AES32DSMI 0x2e000033
> > +#define MASK_AES32DSMI 0x3e00707f
> > +#define MATCH_AES32DSI 0x2a000033
> > +#define MASK_AES32DSI 0x3e00707f
> > +#define MATCH_SHA512SUM0 0x10401013
> > +#define MASK_SHA512SUM0 0xfff0707f
> > +#define MATCH_SHA512SUM1 0x10501013
> > +#define MASK_SHA512SUM1 0xfff0707f
> > +#define MATCH_SHA512SIG0 0x10601013
> > +#define MASK_SHA512SIG0 0xfff0707f
> > +#define MATCH_SHA512SIG1 0x10701013
> > +#define MASK_SHA512SIG1 0xfff0707f
> > +#define MATCH_AES64KS1I 0x31001013
> > +#define MASK_AES64KS1I 0xff00707f
> > +#define MATCH_AES64IM 0x30001013
> > +#define MASK_AES64IM 0xfff0707f
> > +#define MATCH_AES64KS2 0x7e000033
> > +#define MASK_AES64KS2 0xfe00707f
> > +#define MATCH_AES64ESM 0x36000033
> > +#define MASK_AES64ESM 0xfe00707f
> > +#define MATCH_AES64ES 0x32000033
> > +#define MASK_AES64ES 0xfe00707f
> > +#define MATCH_AES64DSM 0x3e000033
> > +#define MASK_AES64DSM 0xfe00707f
> > +#define MATCH_AES64DS 0x3a000033
> > +#define MASK_AES64DS 0xfe00707f
> > /* Privileged CSR addresses. */
> > #define CSR_USTATUS 0x0
> > #define CSR_UIE 0x4
> > @@ -884,6 +952,7 @@
> > #define CSR_TCONTROL 0x7a5
> > #define CSR_MCONTEXT 0x7a8
> > #define CSR_SCONTEXT 0x7aa
> > +#define CSR_SEED 0x015
> > #endif /* RISCV_ENCODING_H */
> > #ifdef DECLARE_INSN
> > DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
> > @@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
> > DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
> > DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
> > DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
> > +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
> > +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
> > +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
> > +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
> > +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
> > DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
> > DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
> > DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
> > @@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
> > DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > +DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
>
> Should the class be CSR_CLASS_ZKR? If so, then we need to update the
> enum riscv_csr_class and riscv_csr_address, to make the -mcsr-check
> option work for zkr extension. For example, added,
>
I am not sure if there need to add a need CSR class, since the ZKR only have one new register, temply I will add it in next version, thanks for the suggestion.
> switch (csr_class)
> {
> case CSR_CLASS_ZKR:
> result = riscv_subset_supports ("zkr");
> need_check_version = false;
> ...
>
> > #endif /* DECLARE_CSR */
> > #ifdef DECLARE_CSR_ALIAS
> > DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > index f61004bdf95..1b5b7cb6ffc 100644
> > --- a/include/opcode/riscv.h
> > +++ b/include/opcode/riscv.h
> > @@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
> > #define OP_MASK_CFUNCT2 0x3
> > #define OP_SH_CFUNCT2 5
> >
> > +/* Scalar crypto fields. */
> > +
> > +#define OP_SH_BS 30
> > +#define OP_MASK_BS 3
> > +#define OP_SH_RNUM 20
> > +#define OP_MASK_RNUM 0xf
> > +
> > /* ABI names for selected x-registers. */
> >
> > #define X_RA 1
> > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> > index 1a094404fc5..9ef6e526690 100644
> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -362,6 +362,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> > print (info->stream, "%s", riscv_gpr_names[rd]);
> > break;
> >
> > + case 'y':
> > + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
> > + break;
> > +
> > case 'z':
> > print (info->stream, "%s", riscv_gpr_names[0]);
> > break;
> > @@ -427,6 +431,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> > break;
> > }
> >
> > + case 'Y':
> > + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
> > + break;
> > +
> > case 'Z':
> > print (info->stream, "%d", rs1);
> > break;
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index b756bae64ab..a8f91e30b51 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
> > #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
> > #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
> > #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_BREV8_32 (0b00111 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_BREV8_64 (0b000111 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
> > #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
>
> Not sure if it is necessary to keep the original M_PERM structure
> here, since these rvbc pseudo IMM can actually be calculated. For
> example, something like,
>
> #define ENCODE_PERM_IMM(xlen, prefix, suffix) \
> (ENCODE_ITYPE_IMM ((((xlen) - 1) & (((xlen) - 1) << (prefix)) & (suffix))))
>
> #define MATCH_PERM_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, -1))
> #define MATCH_PERMP_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, 0x1))
> ...
> #define MATCH_PERM_SHFL_IMM(xlen) (ENCODE_PERM_IMM ((xlen/2), 0, -1))
> ...
> {"rev", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (32),
> MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"rev", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (64),
> MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"orc.p", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (32),
> MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"orc.p", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (64),
> MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> ...
> {"zip", 32, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
> (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"zip", 64, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
> (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> ...
>
> This doesn't really matter for now, but once we have supported the
> whole rvb and rvbk extensions, keeping the M_PERM here may be helpful
> for maintenance. I used to have an internal patch doing something
> similar, if you are interested to complete this, maybe we could
> discuss it in the later mails.
Since there still have a lot of pseudo-instructions with zip/unzip not implement,
like zip2/zip4/zip8/zip.b/zip.n..., so I think keeping the M_PERM is good.
>
> > static int
> > @@ -783,7 +786,7 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> > {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
> >
> > -/* Zbb instructions */
> > +/* Zbb or zbkb instructions */
> > {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
> > {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
> > {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
> > @@ -798,23 +801,30 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
> > {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
> > {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
> > -{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> > -{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> > -{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> > -{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> > -{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> > -{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> > -{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> > -{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > -{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
> > {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
> > {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
> > {"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
> > -{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> > -{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > -{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> > -{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > +{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
>
> The MATCH_SHAMT_BREV8_32 and MATCH_SHAMT_BREV8_64 are the same, so we
> probably don't need two entries but handle the same encoding.
I will merge them in next version, thanks!
>
> > +{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> > +{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> > +{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
> > +{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
> > +{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
> > +{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> > +{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> > +{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> > +{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> > +{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> > +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> > +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> > +{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> > +{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> > +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> >
> > /* Zba instructions */
> > {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> > @@ -828,9 +838,9 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
> > {"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
> >
> > -/* Zbc instructions */
> > -{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> > -{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> > +/* Zbc or zbkc instructions */
> > +{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> > +{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> > {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
> >
> > /* Zbs instructions */
> > @@ -847,6 +857,49 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
> >
> > +/* Zbkx instructions */
> > +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> > +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> > +
> > +/* Zknd instructions */
> > +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> > +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
> > +{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
> > +{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
> > +{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
> > +{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
> > +{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
> > +
> > +/* Zkne instructions */
> > +{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
> > +{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
> > +{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
> > +{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
> > +
> > +/* Zknh instructions */
> > +{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
> > +{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
> > +{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
> > +{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
> > +{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
> > +{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
> > +{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
> > +{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
> > +{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
> > +{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
> > +{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
> > +{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
> > +{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
> > +{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
> > +
> > +/* Zksed instructions */
> > +{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
> > +{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
> > +
> > +/* Zksh instructions */
> > +{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
> > +{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
> > +
> > /* Terminate the list. */
> > {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> > };
> > --
> >
>
> Except the above comments, the encodings should be all correct, so
> this looks good to me.
>
> Thanks
> Nelson
Best wishes
Jiawei</jiawei@iscas.ac.cn></jbeulich@suse.com></schwab@linux-m68k.org></lazyparser@gmail.com></andrew@sifive.com></palmer@dabbelt.com></philipp.tomsich@vrull.eu></jimw@sifive.com></kito.cheng@sifive.com></binutils@sourceware.org></jiawei@iscas.ac.cn></nelson.chu@sifive.com>
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