[PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions
Nelson Chu
nelson.chu@sifive.com
Tue Nov 2 10:38:33 GMT 2021
Hi jiawei,
On Tue, Nov 2, 2021 at 5:44 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> bfd/elfxx-riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cdb4fa0996a..0d8fc755b5c 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1333,7 +1333,7 @@ riscv_compare_subsets (const char *subset1, const char *subset2)
> order1 = riscv_ext_order[(*++subset1 - 'a')];
> order2 = riscv_ext_order[(*++subset2 - 'a')];
> if (order1 != order2)
> - return order1 - order2;
> + return order2 - order1;
> }
> return strcasecmp (++subset1, ++subset2);
> }
> --
> 2.25.1
>
After I apply this change, I get the unexpected results as follows,
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
-misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
Assembler messages:
Error: rv64i_zicsr_zifencei_zbb: prefixed ISA extension `zbb' is not
in expected order. It must come before `zifencei'
BTW, the expected result is as follows, before applying this patch,
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
-misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-readelf
-A empty.o Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p1_zicsr2p0_zifencei2p0_zbb1p0"
Could I ask what issues or cases you want to resolve originally, so
that you need to change this?
Thanks
Nelson
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