[committed 11/18] MIPS/opcodes: Disassemble the RFE instruction

[Maciej W. Rozycki]

Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression 
and bring the disassembly of the RFE instruction back for the relevant 
ISA levels.

It is because the "rfe" opcode table entry was incorrectly moved behind 
the catch-all generic "c0" entry for CP0 instructions, causing output 
like:

  00:	42000010 	c0	0x10

to be produced rather than:

  00:	42000010 	rfe

even for ISA levels that do include the RFE instruction.

Move the "rfe" entry ahead of "c0" then, correcting the problem.  Add a 
suitable test case.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead 
	of "c0".

	gas/
	* testsuite/gas/mips/rfe.d: New test.
	* testsuite/gas/mips/rfe.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.
---
 gas/testsuite/gas/mips/mips.exp |    3 +++
 gas/testsuite/gas/mips/rfe.d    |    9 +++++++++
 gas/testsuite/gas/mips/rfe.s    |    8 ++++++++
 opcodes/mips-opc.c              |    5 +++--
 4 files changed, 23 insertions(+), 2 deletions(-)

binutils-mips-opcodes-rfe.diff
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1338,6 +1338,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "cp0m"		[mips_arch_list_matching mips1 \
 					    !mips2 !micromips]
 
+    run_dump_test_arches "rfe"		[mips_arch_list_matching mips1 \
+					    !mips3 !mips32 !micromips]
+
     run_dump_test "cp1-names-numeric"
     run_dump_test "cp1-names-r3000"
     run_dump_test "cp1-names-r3900"
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.d
@@ -0,0 +1,9 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000010 	rfe
+	\.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.s
@@ -0,0 +1,8 @@
+	.text
+	.set	noreorder
+foo:
+	rfe
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -3399,6 +3399,9 @@ const struct mips_opcode mips_builtin_op
 {"ginvi",		"s",		0x7c00003d, 0xfc1fffff, RD_1,			0,		0,		GINV,	0 },
 {"ginvt",		"s,+\\",	0x7c0000bd, 0xfc1ffcff, RD_1,			0,		0,		GINV,	0 },
 
+/* RFE conflicts with the new Virt spec instruction tlbgp. */
+{"rfe",			"",		0x42000010, 0xffffffff,	0,			0,		I1|T3,		0,	0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
@@ -3411,8 +3414,6 @@ const struct mips_opcode mips_builtin_op
 {"cop1",		"C",		0,    (int) M_COP1,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"cop2",		"C",		0,    (int) M_COP2,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
 {"cop3",		"C",		0,    (int) M_COP3,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-/* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe",			"",		0x42000010, 0xffffffff,	0,			0,		I1|T3,		0,	0 },
 };
 
 #define MIPS_NUM_OPCODES \