[committed 00/18] MIPS coprocessor opcodes handling fixes

[Maciej W. Rozycki]

Hi,

 In the course of an attempt to track down a Linux kernel heisenbug making 
init(8) sometimes crash with SIGSEGV upon boot with an R3000-based system 
I have noticed the RFE instruction is not correctly disassembled and the 
generic `c0 0x10' notation is produced instead.  This is due to an earlier 
change, which reordered the "rfe" entry in the opcode table to the wrong 
place and caused this regression.

 This was supposed to be a simple change, a one-liner really, but I chose 
to add a proper test case for it and in the course I discovered numerous 
issues in coprocessor opcode handling, plus a missing `config.sub' part 
required for some GAS configurations, already committed previously.  I 
ended up with this patch series of 18 patches total, with the original RFE 
fix buried within, as 11/18.  Also I had 1/18 prepared earlier on already, 
but it's turned out intertwined with some of the other changes, so I have 
bundled it with the rest.

 See individual change descriptions for details.

 Regression-tested across 87 MIPS targets.  Committed.

  Maciej