[Integration 5/6] RISC-V/zfh: Add half-precision floating-point v0.1 instructions.
Jim Wilson
jimw@sifive.com
Tue Mar 30 23:09:50 GMT 2021
On Tue, Mar 30, 2021 at 2:37 AM Nelson Chu <nelson.chu@sifive.com> wrote:
> +#define MATCH_FCVT_Q_H 0x46300053
> +#define MASK_FCVT_Q_H 0xfff0007f
> +#define MATCH_FCVT_H_Q 0x44200053
> +#define MASK_FCVT_H_Q 0xfff0007f
>
This looks wrong. I think fcvt.q.h should be 0x462 and fcvt.h.q should be
0x443. SiFive doesn't have Q support, so this wouldn't have turned up in
internal testing.
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 10e60fd..5a4f7bb 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -492,6 +492,9 @@ enum riscv_extended_insn_class
> INSN_CLASS_V_AND_F,
> INSN_CLASS_V_OR_ZVAMO,
> INSN_CLASS_V_OR_ZVLSSEG,
> + INSN_CLASS_F_AND_ZFH,
>
This F and ZFH class looks redundant. Zfh implies f just like d does. We
don't need a F_AND_D class, so we don't need a F_AND_ZFH class. It does no
harm though.
There is also a zfhmin extension in the docs I'm looking at. That would
require another insn class. But we can always add this later.
Jim
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