[Integration 3/6] RISC-V/sifive: Add sifive cache control instructions.

[Jim Wilson]

On Tue, Mar 30, 2021 at 2:37 AM Nelson Chu <nelson.chu@sifive.com> wrote:

> +#as:
> -march=rv32i_xsifivecdiscarddlone_xsifivecflushdlone_xsifivecflushilone


This looks awkward.  Maybe we can add xsifive as an extension that implies
the other 3.
Jim