On Wed, Mar 24, 2021 at 2:21 AM Jan Beulich <jbeulich@suse.com> wrote: > > 1: limit breakage from gcc movdir64b et al workaround > 2: fix AMD Zen3 insns > 3: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear > 4: flag bad S/G insn operand combinations > OK for all. Thanks. -- H.J.