[RFC] SVP64 Cray-style Vectorisation of the OpenPOWER scalar ISA

[lkcl]

On Monday, March 22, 2021, lkcl <luke.leighton@gmail.com> wrote:

>
> ah.  right.  so it would be genuinely the case... let me test it...
>            'addi 4+1, 3, 1',
> yep that actually works.
>
> that one we're going to have to ask David and Segher about, to see if
> gcc-rs6000.md generates registers-as-expressions.
>


https://libre-soc.org/irclog/%23libre-soc.2021-03-22.log.html#t2021-03-22T16:17:55

segher kindly informs us that gcc-ppc calculate reg nums itself: no
register-nums-as-gas-expressions.

i can live with people getting syntax errors if they try "8.v/4" or "8/4.v"
or such in svp64.

l.