[PATCH 3/8] x86: don't use opcode_length to identify pseudo prefixes
H.J. Lu
hjl.tools@gmail.com
Mon Mar 22 17:55:50 GMT 2021
On Mon, Mar 22, 2021 at 9:43 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> This is in preparation of opcode_length going away as a field in the
> templates. Identify pseudo prefixes by a base opcode of zero instead:
> No real prefix has an opcode of zero. This at the same time allow
> dropping a curious special case from i386-gen.
>
> gas/
> 2021-03-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (parse_insn): Recognize pseudo prefixes by
> base_opcode and extension_opcode.
>
> opcodes/
> 2021-03-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
> check.
> * i386-opc.h (Prefix_*): Move #define-s.
> * i386-opc.tbl: Move pseudo prefix enumerator values to
> extension opcode field.
> * i386-tbl.h: Re-generate.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -5123,10 +5123,11 @@ parse_insn (char *line, char *mnemonic)
> current_templates->start->name);
> return NULL;
> }
> - if (current_templates->start->opcode_length == 0)
> +
> + if (current_templates->start->base_opcode == 0)
> {
> /* Handle pseudo prefixes. */
> - switch (current_templates->start->base_opcode)
> + switch (current_templates->start->extension_opcode)
> {
> case Prefix_Disp8:
> /* {disp8} */
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -1208,8 +1208,7 @@ process_i386_opcode_modifier (FILE *tabl
> || strncasecmp(str, "EVex=", 5) == 0
> || strncasecmp(str, "Disp8MemShift=", 14) == 0
> || strncasecmp(str, "Masking=", 8) == 0
> - || strcasecmp(str, "SAE") == 0
> - || strcasecmp(str, "IsPrefix") == 0)
> + || strcasecmp(str, "SAE") == 0)
> regular_encoding = 0;
>
> set_bitfield (str, modifiers, val, ARRAY_SIZE (modifiers),
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -920,6 +920,14 @@ typedef struct insn_template
> #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
> #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
>
> + /* extension_opcode is the 3 bit extension for group <n> insns.
> + This field is also used to store the 8-bit opcode suffix for the
> + AMD 3DNow! instructions.
> + If this template has no extension opcode (the usual case) use None
> + Instructions */
> + unsigned short extension_opcode;
> +#define None 0xffff /* If no extension_opcode is possible. */
> +
> /* Pseudo prefixes. */
> #define Prefix_Disp8 0 /* {disp8} */
> #define Prefix_Disp16 1 /* {disp16} */
> @@ -932,14 +940,6 @@ typedef struct insn_template
> #define Prefix_REX 8 /* {rex} */
> #define Prefix_NoOptimize 9 /* {nooptimize} */
>
> - /* extension_opcode is the 3 bit extension for group <n> insns.
> - This field is also used to store the 8-bit opcode suffix for the
> - AMD 3DNow! instructions.
> - If this template has no extension opcode (the usual case) use None
> - Instructions */
> - unsigned short extension_opcode;
> -#define None 0xffff /* If no extension_opcode is possible. */
> -
> /* Opcode length. */
> unsigned char opcode_length;
>
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -849,19 +849,19 @@ rex.wrb, 0x4d, None, 1, Cpu64, No_bSuf|N
> rex.wrx, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> rex.wrxb, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
>
> -// Pseudo prefixes (opcode_length == 0)
> +// Pseudo prefixes (base_opcode == 0)
>
> -{disp8}, Prefix_Disp8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{disp16}, Prefix_Disp16, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{disp32}, Prefix_Disp32, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{load}, Prefix_Load, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{store}, Prefix_Store, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{vex}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{vex2}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{vex3}, Prefix_VEX3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{evex}, Prefix_EVEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{rex}, Prefix_REX, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> -{nooptimize}, Prefix_NoOptimize, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{disp8}, 0, Prefix_Disp8, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{disp16}, 0, Prefix_Disp16, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{disp32}, 0, Prefix_Disp32, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{load}, 0, Prefix_Load, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{store}, 0, Prefix_Store, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{vex}, 0, Prefix_VEX, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{vex2}, 0, Prefix_VEX, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{vex3}, 0, Prefix_VEX3, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{evex}, 0, Prefix_EVEX, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{rex}, 0, Prefix_REX, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
> +{nooptimize}, 0, Prefix_NoOptimize, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
Please define an opcode macro for pseudo prefix, something like
#define PSEUDO_PREFIX 0
Thanks.
--
H.J.
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