[PATCH 1/8] x86: unbreak certain MPX insn operand forms
Jan Beulich
jbeulich@suse.com
Mon Mar 22 16:42:18 GMT 2021
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX
base_opcode") dropped the mandatory prefix bytes from legacy encoded
insn templates, but failed to also adjust affected MPX-specific checks
in two places.
For the expressions to remain halfway readable, introduce local
variables to hold current_templates->start.
gas/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_index_check): New local variable t.
Correct MPX insn check.
* config/tc-i386-intel.c (i386_intel_simplify_register): Correct
MPX insn check.
* testsuite/gas/i386/x86-64-mpx.s: Add RIP-relative cases. Test
index scaling by other than 1.
* testsuite/gas/i386/x86-64-mpx.d: Adjust expectations.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -314,9 +314,13 @@ i386_intel_simplify_register (expression
intel_state.base = i386_regtab + reg_num;
else if (!intel_state.index)
{
+ const insn_template *t = current_templates->start;
+
if (intel_state.in_scale
- || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
- || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
+ || (t->opcode_modifier.opcodeprefix == PREFIX_0XF3
+ && t->base_opcode == 0x0f1b /* bndmk */)
+ || (t->opcode_modifier.opcodeprefix == PREFIX_NONE
+ && (t->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */)
|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
intel_state.index = i386_regtab + reg_num;
else
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -11031,9 +11031,10 @@ i386_index_check (const char *operand_st
{
const char *kind = "base/index";
enum flag_code addr_mode = i386_addressing_mode ();
+ const insn_template *t = current_templates->start;
- if (current_templates->start->opcode_modifier.isstring
- && !current_templates->start->cpu_flags.bitfield.cpupadlock
+ if (t->opcode_modifier.isstring
+ && !t->cpu_flags.bitfield.cpupadlock
&& (current_templates->end[-1].opcode_modifier.isstring
|| i.mem_operands))
{
@@ -11050,7 +11051,7 @@ i386_index_check (const char *operand_st
kind = "string address";
- if (current_templates->start->opcode_modifier.prefixok == PrefixRep)
+ if (t->opcode_modifier.prefixok == PrefixRep)
{
int es_op = current_templates->end[-1].opcode_modifier.isstring
- IS_STRING_ES_OP0;
@@ -11130,9 +11131,11 @@ i386_index_check (const char *operand_st
goto bad_address;
/* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
- if (current_templates->start->base_opcode == 0xf30f1b
- || (current_templates->start->base_opcode & ~1) == 0x0f1a
- || current_templates->start->opcode_modifier.sib == SIBMEM)
+ if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3
+ && t->base_opcode == 0x0f1b)
+ || (t->opcode_modifier.opcodeprefix == PREFIX_NONE
+ && (t->base_opcode & ~1) == 0x0f1a)
+ || t->opcode_modifier.sib == SIBMEM)
{
/* They cannot use RIP-relative addressing. */
if (i.base_reg && i.base_reg->reg_num == RegIP)
@@ -11142,7 +11145,8 @@ i386_index_check (const char *operand_st
}
/* bndldx and bndstx ignore their scale factor. */
- if ((current_templates->start->base_opcode & ~1) == 0x0f1a
+ if (t->opcode_modifier.opcodeprefix == PREFIX_NONE
+ && (t->base_opcode & ~1) == 0x0f1a
&& i.log2_scale_factor)
as_warn (_("register scaling is being ignored here"));
}
--- a/gas/testsuite/gas/i386/x86-64-mpx.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -14,16 +14,17 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1b 48 03 bndmk 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 0c 25 03 00 00 00 bndmk 0x3\(,%r12,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%rax,%rcx,1\),%bnd1
-[ ]*[a-f0-9]+: f3 41 0f 1b 4c 03 03 bndmk 0x3\(%r11,%rax,1\),%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1b 4c 43 03 bndmk 0x3\(%r11,%rax,2\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 4c 0b 03 bndmk 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 0b bndmov \(%r11\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%rax\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0c 25 99 03 00 00 bndmov 0x399,%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 51 03 bndmov 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 50 03 bndmov 0x3\(%rax\),%bnd2
+[ ]*[a-f0-9]+: 66 0f 1a 15 33 33 00 00 bndmov 0x3333\(%rip\),%bnd2 ?.*
[ ]*[a-f0-9]+: 66 42 0f 1a 04 25 03 00 00 00 bndmov 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: 66 0f 1a 14 10 bndmov \(%rax,%rdx,1\),%bnd2
-[ ]*[a-f0-9]+: 66 41 0f 1a 4c 03 03 bndmov 0x3\(%r11,%rax,1\),%bnd1
+[ ]*[a-f0-9]+: 66 41 0f 1a 4c 43 03 bndmov 0x3\(%r11,%rax,2\),%bnd1
[ ]*[a-f0-9]+: 66 42 0f 1a 4c 0b 03 bndmov 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
[ ]*[a-f0-9]+: 66 41 0f 1b 0b bndmov %bnd1,\(%r11\)
@@ -31,9 +32,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1b 0c 25 99 03 00 00 bndmov %bnd1,0x399
[ ]*[a-f0-9]+: 66 41 0f 1b 51 03 bndmov %bnd2,0x3\(%r9\)
[ ]*[a-f0-9]+: 66 0f 1b 50 03 bndmov %bnd2,0x3\(%rax\)
+[ ]*[a-f0-9]+: 66 0f 1b 15 33 33 00 00 bndmov %bnd2,0x3333\(%rip\) ?.*
[ ]*[a-f0-9]+: 66 42 0f 1b 04 25 03 00 00 00 bndmov %bnd0,0x3\(,%r12,1\)
[ ]*[a-f0-9]+: 66 0f 1b 14 10 bndmov %bnd2,\(%rax,%rdx,1\)
-[ ]*[a-f0-9]+: 66 41 0f 1b 4c 03 03 bndmov %bnd1,0x3\(%r11,%rax,1\)
+[ ]*[a-f0-9]+: 66 41 0f 1b 4c 43 03 bndmov %bnd1,0x3\(%r11,%rax,2\)
[ ]*[a-f0-9]+: 66 42 0f 1b 4c 0b 03 bndmov %bnd1,0x3\(%rbx,%r9,1\)
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
@@ -43,9 +45,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
+[ ]*[a-f0-9]+: f3 0f 1a 15 33 33 00 00 bndcl 0x3333\(%rip\),%bnd2 ?.*
[ ]*[a-f0-9]+: f3 42 0f 1a 04 25 03 00 00 00 bndcl 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f3 0f 1a 14 10 bndcl \(%rax,%rdx,1\),%bnd2
-[ ]*[a-f0-9]+: f3 41 0f 1a 4c 03 03 bndcl 0x3\(%r11,%rax,1\),%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1a 4c 43 03 bndcl 0x3\(%r11,%rax,2\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
@@ -54,9 +57,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
+[ ]*[a-f0-9]+: f2 0f 1a 15 33 33 00 00 bndcu 0x3333\(%rip\),%bnd2 ?.*
[ ]*[a-f0-9]+: f2 42 0f 1a 04 25 03 00 00 00 bndcu 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f2 0f 1a 14 10 bndcu \(%rax,%rdx,1\),%bnd2
-[ ]*[a-f0-9]+: f2 41 0f 1a 4c 03 03 bndcu 0x3\(%r11,%rax,1\),%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1a 4c 43 03 bndcu 0x3\(%r11,%rax,2\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
@@ -65,9 +69,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
+[ ]*[a-f0-9]+: f2 0f 1b 15 33 33 00 00 bndcn 0x3333\(%rip\),%bnd2 ?.*
[ ]*[a-f0-9]+: f2 42 0f 1b 04 25 03 00 00 00 bndcn 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f2 0f 1b 14 10 bndcn \(%rax,%rdx,1\),%bnd2
-[ ]*[a-f0-9]+: f2 41 0f 1b 4c 03 03 bndcn 0x3\(%r11,%rax,1\),%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1b 4c 43 03 bndcn 0x3\(%r11,%rax,2\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1b 4c 0b 03 bndcn 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%rax,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%rbx,%rdx,1\)
@@ -85,11 +90,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 25 02 00 00 bnd call 416 <foo>
+[ ]*[a-f0-9]+: f2 e8 25 02 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%rax\)
[ ]*[a-f0-9]+: f2 41 ff 13 bnd call \*\(%r11\)
-[ ]*[a-f0-9]+: f2 0f 84 17 02 00 00 bnd je 416 <foo>
-[ ]*[a-f0-9]+: f2 e9 11 02 00 00 bnd jmp 416 <foo>
+[ ]*[a-f0-9]+: f2 0f 84 17 02 00 00 bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 e9 11 02 00 00 bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%rcx\)
[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmp \*\(%r12\)
[ ]*[a-f0-9]+: f2 c3 bnd ret *
@@ -171,11 +176,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd call 416 <foo>
+[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%rax
[ ]*[a-f0-9]+: f2 41 ff d3 bnd call \*%r11
-[ ]*[a-f0-9]+: f2 74 0c bnd je 416 <foo>
-[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 416 <foo>
+[ ]*[a-f0-9]+: f2 74 0c bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 eb 09 bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%rcx
[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmp \*%r12
[ ]*[a-f0-9]+: f2 c3 bnd ret *
--- a/gas/testsuite/gas/i386/x86-64-mpx.s
+++ b/gas/testsuite/gas/i386/x86-64-mpx.s
@@ -10,7 +10,7 @@ start:
bndmk 0x3(%rax), %bnd1
bndmk 0x3(,%r12,1), %bnd1
bndmk (%rax,%rcx), %bnd1
- bndmk 0x3(%r11,%rax,1), %bnd1
+ bndmk 0x3(%r11,%rax,2), %bnd1
bndmk 0x3(%rbx,%r9,1), %bnd1
### bndmov
@@ -19,9 +19,10 @@ start:
bndmov (0x399), %bnd1
bndmov 0x3(%r9), %bnd2
bndmov 0x3(%rax), %bnd2
+ bndmov 0x3333(%rip), %bnd2
bndmov 0x3(,%r12,1), %bnd0
bndmov (%rax,%rdx), %bnd2
- bndmov 0x3(%r11,%rax,1), %bnd1
+ bndmov 0x3(%r11,%rax,2), %bnd1
bndmov 0x3(%rbx,%r9,1), %bnd1
bndmov %bnd2, %bnd0
@@ -30,9 +31,10 @@ start:
bndmov %bnd1, (0x399)
bndmov %bnd2, 0x3(%r9)
bndmov %bnd2, 0x3(%rax)
+ bndmov %bnd2, 0x3333(%rip)
bndmov %bnd0, 0x3(,%r12,1)
bndmov %bnd2, (%rax,%rdx)
- bndmov %bnd1, 0x3(%r11,%rax,1)
+ bndmov %bnd1, 0x3(%r11,%rax,2)
bndmov %bnd1, 0x3(%rbx,%r9,1)
bndmov %bnd0, %bnd2
@@ -44,9 +46,10 @@ start:
bndcl (0x399), %bnd1
bndcl 0x3(%r9), %bnd2
bndcl 0x3(%rax), %bnd2
+ bndcl 0x3333(%rip), %bnd2
bndcl 0x3(,%r12,1), %bnd0
bndcl (%rax,%rdx), %bnd2
- bndcl 0x3(%r11,%rax,1), %bnd1
+ bndcl 0x3(%r11,%rax,2), %bnd1
bndcl 0x3(%rbx,%r9,1), %bnd1
### bndcu
@@ -57,9 +60,10 @@ start:
bndcu (0x399), %bnd1
bndcu 0x3(%r9), %bnd2
bndcu 0x3(%rax), %bnd2
+ bndcu 0x3333(%rip), %bnd2
bndcu 0x3(,%r12,1), %bnd0
bndcu (%rax,%rdx), %bnd2
- bndcu 0x3(%r11,%rax,1), %bnd1
+ bndcu 0x3(%r11,%rax,2), %bnd1
bndcu 0x3(%rbx,%r9,1), %bnd1
### bndcn
@@ -70,9 +74,10 @@ start:
bndcn (0x399), %bnd1
bndcn 0x3(%r9), %bnd2
bndcn 0x3(%rax), %bnd2
+ bndcn 0x3333(%rip), %bnd2
bndcn 0x3(,%r12,1), %bnd0
bndcn (%rax,%rdx), %bnd2
- bndcn 0x3(%r11,%rax,1), %bnd1
+ bndcn 0x3(%r11,%rax,2), %bnd1
bndcn 0x3(%rbx,%r9,1), %bnd1
### bndstx
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