[RFC] SVP64 Cray-style Vectorisation of the OpenPOWER scalar ISA

[lkcl]

On Fri, Mar 19, 2021 at 11:45 AM lkcl <luke.leighton@gmail.com> wrote:

> you can see where i'm going with that: these are register names.
> if "f 0" or "vr 5" is a syntax error then logically so is "r0 .v".
> worth testing "addi r 0, r  1, 5"?

enabling -mregnames, below is gnu-as 2.35.1 (debian)

* spaces in standard register names create a syntax error.
* division works when it's a straight number (immediate)
* add - even when it's a register number (5+3) - works!
* add - when it's a register operand (r5+3) - does *not* work.

conclusion: "/" definitely not ok in operands, also probably ok with
"r0.v" no spaces.

l.


https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simulator/program.py;hb=HEAD
            ....
            args = ["powerpc64-linux-gnu-as",
                    '-mpower9',
                    '-mregnames',
                    self.obj_fmt,
                    "-o",

lkcl@fizzy:~/src/libresoc/soc/src/soc$ python3 simulator/program.py
{standard input}: Assembler messages:
{standard input}:4: Error: syntax error; found `2', expected `,'
{standard input}:4: Error: junk at end of line: `2,3,1'
{standard input}:4: Error: unsupported relocation against r
Error in program:
addi 5, 0, 4660/2        <- this seems ok
mtcrf 255, 5+3          <- so is this!
mfocrf 2, 1
addi r 2, 3, 1              <- space here isn't ok
attn