[Patch, Gas, AArch64][1/1] Reclassify Armv8.7-A ST/LD64 Atomics.

[Tejas Belagod]

Hi,

This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl according to their encoding class as specified in the architecture. This also has the fortunate side-effect of spurious unpredictable warnings getting eliminated.

For eg. For instruction:
        st64bv  x0, x2, [x0]

We incorrectly warn when its not necessary:

t.s:8: Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]'

This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. This patch fixes it by reclassifying it and no warnings are issued for this instruction.

Tested on master with make check on binutils. OK for master?

Thanks,
Tejas.

opcodes/ChangeLog:

2021-03-11  Tejas Belagod  <tejas.belagod@arm.com>

	* aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
	LD64/ST64 instructions to lse_atomic instead of ldstexcl.
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