[PATCH 0/9] x86: disassembler fixes and table shrinking

H.J. Lu hjl.tools@gmail.com
Tue Mar 9 14:27:12 GMT 2021


On Tue, Mar 9, 2021 at 5:05 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> The first and last patches are bug fixes. Most of the others
> rearrange the order of decoding of relevant parts of the insn,
> with the goal of shrinking overall table sizes. This goes
> along the lines of earlier changes towards the same goal.
>
> If I had recognized earlier the issue the last patch fixes, I
> would have put it near the beginning of this series. Re-
> basing ahead, however, turned out rather undesirable.
>
> 1: correct decoding of nop/reserved space (0f18 ... 0x1f)
> 2: re-arrange order of decode for various legacy opcodes
> 3: re-arrange order of decode for various VEX opcodes
> 4: re-arrange order of decode for various mask reg opcodes
> 5: re-arrange order of decode for various EVEX opcodes
> 6: reuse VEX entries for EVEX vperm{q,pd}
> 7: reuse further VEX entries for EVEX
> 8: rearrange enumerator and table entry order
> 9: Intel: correct AVX512 S/G disassembly
>

OK for all.

Thanks.

-- 
H.J.


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