PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension
Andrea Corallo
andrea.corallo@arm.com
Tue Jul 20 15:41:23 GMT 2021
Hi all,
second patch of the series adding support for PACBTI for Cortex-M.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
This is to add the 'pacbti' instruction.
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
-------------- next part --------------
>From 4ba39f4a330536462eaa7f8432ee5491159833b1 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Tue, 18 May 2021 11:28:17 +0200
Subject: [PATCH 02/10] PATCH [2/10] arm: add 'pacbti' instruction for
Armv8.1-M pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c
(enum operand_parse_code): Add OP_SP and OP_R12.
(parse_operands): Add switch cases for OP_SP and OP_R12.
(T16_32_TAB): Add '_pacbti'.
(do_t_pacbti): New function.
(insns): Add 'pacbti'.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
---
gas/config/tc-arm.c | 22 ++++++++++++++++++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d | 4 ++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l | 4 ++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s | 8 +++++++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
7 files changed, 42 insertions(+)
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d7f8fca803b..ed870f01aee 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7115,6 +7115,8 @@ enum operand_parse_code
/* New operands for Armv8.1-M Mainline. */
OP_LR, /* ARM LR register */
+ OP_SP, /* ARM SP register */
+ OP_R12,
OP_RRe, /* ARM register, only even numbered. */
OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
@@ -7425,6 +7427,8 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
case OP_RRo:
case OP_LR:
case OP_oLR:
+ case OP_SP:
+ case OP_R12:
case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
@@ -8122,6 +8126,16 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
inst.error = _("operand must be LR register");
break;
+ case OP_SP:
+ if (inst.operands[i].reg != REG_SP)
+ inst.error = _("operand must be SP register");
+ break;
+
+ case OP_R12:
+ if (inst.operands[i].reg != REG_R12)
+ inst.error = _("operand must be r12");
+ break;
+
case OP_RMQRZ:
case OP_oRMQRZ:
case OP_RR_ZR:
@@ -11491,6 +11505,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_negs, 4240, f1d00000), /* rsbs #0 */ \
X(_orr, 4300, ea400000), \
X(_orrs, 4300, ea500000), \
+ X(_pacbti, 0000, f3af800d), \
X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
X(_push, b400, e92d0000), /* stmdb sp!,... */ \
X(_rev, ba00, fa90f080), \
@@ -22317,6 +22332,12 @@ do_vmmla (void)
neon_three_args (1);
}
+static void
+do_t_pacbti (void)
+{
+ inst.instruction = THUMB_OP32 (inst.instruction);
+}
+
/* Overall per-instruction processing. */
@@ -26306,6 +26327,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
ToU("bti", f3af800f, 0, (), noargs),
+ toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
new file mode 100644
index 00000000000..5b040eab118
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M pointer authentication and branch target identification extention
+#source: armv8_1-m-pacbti-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-pacbti-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
new file mode 100644
index 00000000000..a812603d88d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:6: Error: operand must be r12 -- `pacbti r11,lr,sp'
+.*:7: Error: operand must be LR register -- `pacbti r12,r10,sp'
+.*:8: Error: operand must be SP register -- `pacbti r12,lr,r10'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
new file mode 100644
index 00000000000..64e71e70c11
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
@@ -0,0 +1,8 @@
+ .syntax unified
+ .text
+ .thumb
+.Lstart:
+ bti
+ pacbti r11, lr, sp
+ pacbti r12, r10, sp
+ pacbti r12, lr, r10
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 3c693728468..593ac34ed49 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -7,4 +7,5 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 800f bti
+0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 38929e3dd02..39db4542e39 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -3,3 +3,4 @@
.thumb
.Lstart:
bti
+ pacbti r12, lr, sp
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 1e096997543..34b0ace58bc 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4656,6 +4656,8 @@ static const struct opcode32 thumb32_opcodes[] =
Identification Extension. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
instructions. */
--
2.20.1
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