[PATCH v3] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).

[Jan Beulich]

On 07.01.2021 04:49, Nelson Chu wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
> @@ -0,0 +1,58 @@
> +	# pseudo/aliaese
> +	zext.h	a0, a1
> +	rev8	a0, a1
> +	orc.b	a0, a1
> +.ifdef __64_bit__
> +	zext.w	a0, a1
> +.endif
> +
> +	# ZBA
> +	sh1add	a0, a1, a2
> +	sh2add	a0, a1, a2
> +	sh3add	a0, a1, a2
> +.ifdef __64_bit__
> +	sh1add.uw	a0, a1, a2
> +	sh2add.uw	a0, a1, a2
> +	sh3add.uw	a0, a1, a2
> +	add.uw		a0, a1, a2
> +	slli.uw		a0, a1, 0
> +	slli.uw		a0, a1, 63
> +.endif
> +
> +	# ZBB
> +	clz	a0, a1
> +	ctz	a0, a1
> +	cpop	a0, a1
> +	min	a0, a1, a2
> +	max	a0, a1, a2
> +	minu	a0, a1, a2
> +	maxu	a0, a1, a2
> +	sext.b	a0, a1
> +	sext.h	a0, a1
> +	andn	a0, a1, a2
> +	orn	a0, a1, a2
> +	xor	a0, a1, a2

Wasn't this meant to be xnor?

> @@ -502,6 +499,54 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"remw",     64, INSN_CLASS_M, "d,s,t",  MATCH_REMW, MASK_REMW, match_opcode, 0 },
>  {"remuw",    64, INSN_CLASS_M, "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
>  
> +/* Bitmanip instruction subset - ZBA/ZBB/ZBC  */
> +{"sh1add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> +{"sh2add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
> +{"sh3add",    0, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
> +{"sh1add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
> +{"sh2add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
> +{"sh3add.uw",64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
> +{"zext.w",   64, INSN_CLASS_ZBA_OR_ZBB,   "d,s",    MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
> +{"zext.w",   64, INSN_CLASS_I,     "d,s",    0, (int) M_ZEXTW,  match_never, INSN_MACRO },
> +{"add.uw",   64, INSN_CLASS_ZBA,   "d,s,t",  MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
> +{"slli.uw",  64, INSN_CLASS_ZBA,   "d,s,>",  MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },

For consistency with other insns taking immediate operands,
shouldn't this one have a sll.uw alias?

Also two perhaps more spec related questions: Why does slli.uw
allow for 7-bit wide shamt? Any shift count 32 and up is not
in need of this new insn, as slli will yield the same result.
(I could see the need in RV128, where counts up to 95 would be
needed, but right now talk is - I take it - mainly of RV32 and
RV64.)

The current draft also doesn't say anything about hints; one
could destination being x0 may get treated the same as in the
base spec, but in the absence of this being said explicitly
one could as well imply these are all simply sort-of-nop-s, or
even illegal.

Jan