[PATCH v2 2/2] RISC-V: Support aliases for frozen Zbs instructions (v0.94-draft)

[Philipp Tomsich]

Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
encode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.

Suggested-by: Jan Beulich <jbeulich@suse.com>

2021-01-11  Philipp Tomsich  <philipp.tomsich@vrull.eu>

        gas/
            * testsuite/gas/riscv/bitmanip-insns-32.d: Add tests.
            * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
            * testsuite/gas/riscv/bitmanip-insns.s: Likewise.
        opcodes/
            * riscv-opc.c (riscv_opcodes): Add aliases for Zbs.

---

Changes in v2:
- Add aliases for the b{set,clr,inv,ext} when called with an immediate
  as a second source operand.

 gas/testsuite/gas/riscv/bitmanip-insns-32.d |  4 ++++
 gas/testsuite/gas/riscv/bitmanip-insns-64.d |  8 ++++++++
 gas/testsuite/gas/riscv/bitmanip-insns.s    | 11 +++++++++++
 opcodes/riscv-opc.c                         |  4 ++++
 4 files changed, 27 insertions(+)

diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
index d9fd662..0e8243d 100644
--- a/gas/testsuite/gas/riscv/bitmanip-insns-32.d
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
@@ -47,3 +47,7 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
index 758c47f..0dbf7ae 100644
--- a/gas/testsuite/gas/riscv/bitmanip-insns-64.d
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
@@ -69,3 +69,11 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclri[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bseti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binvi[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bexti[ 	]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
index caf8475..0187eda 100644
--- a/gas/testsuite/gas/riscv/bitmanip-insns.s
+++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
@@ -76,3 +76,14 @@
 	bset	a0, a1, a2
 	binv	a0, a1, a2
 	bext	a0, a1, a2
+	# aliases
+	bclr	a0, a1, 31
+	bset	a0, a1, 31
+	binv	a0, a1, 31
+	bext	a0, a1, 31
+.ifdef __64_bit__
+	bclr	a0, a1, 63
+	bset	a0, a1, 63
+	binv	a0, a1, 63
+	bext	a0, a1, 63
+.endif
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0d903dd..3e89145 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -553,9 +553,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
 {"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
 {"bclr",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+{"bclr",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
 {"bset",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BSET, MASK_BSET, match_opcode, 0 },
+{"bset",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
 {"binv",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BINV, MASK_BINV, match_opcode, 0 },
+{"binv",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
 {"bext",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+{"bext",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
 
 /* Single-precision floating-point instruction subset */
 {"frcsr",     0, INSN_CLASS_F,   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-- 
1.8.3.1