[PATCH] RISC-V: Support riscv bitmanip frozen Zbs instructions (v0.94-draft)

[Philipp Tomsich]

Jan,

I kept the initial enablement minimal on purpose: the goal was to have the
architecturally
defined instructions available and minimize the surface for testing (the
compiler had to be
changed over to the removal of w-form instructions in parallel).

I'll make this a two-patch series for v2, so we implement whatever the
consensus on
these aliases will be at apply-time.

Thanks for the review,
Philipp.


On Mon, 11 Jan 2021 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:

> On 09.01.2021 16:54, Philipp Tomsich wrote:
> > @@ -548,6 +548,15 @@ const struct riscv_opcode riscv_opcodes[] =
> >  {"clmulh",    0, INSN_CLASS_ZBC,   "d,s,t",  MATCH_CLMULH, MASK_CLMULH,
> match_opcode, 0 },
> >  {"clmulr",    0, INSN_CLASS_ZBC,   "d,s,t",  MATCH_CLMULR, MASK_CLMULR,
> match_opcode, 0 },
> >
> > +{"bclri",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI,
> match_opcode, 0 },
> > +{"bseti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI,
> match_opcode, 0 },
> > +{"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI,
> match_opcode, 0 },
> > +{"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI,
> match_opcode, 0 },
> > +{"bclr",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BCLR, MASK_BCLR,
> match_opcode, 0 },
> > +{"bset",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BSET, MASK_BSET,
> match_opcode, 0 },
> > +{"binv",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BINV, MASK_BINV,
> match_opcode, 0 },
> > +{"bext",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BEXT, MASK_BEXT,
> match_opcode, 0 },
>
> Following other insns with immediate operands, shouldn't there be
> INSN_ALIAS entries here for the respective entries with the trailing
> 'i' omitted from the mnemonic?
>
> Jan
>