[PATCH] RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions

[Jan Beulich]

On 24.02.2021 09:50, Kuan-Lin Chen via Binutils wrote:
> This patch is to support bitmanip-0.93 ZBA/ZBB/ZBC extensions.
> 
> bfd/
>          * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
> 
> gas/
>          * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
>          (riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
>          * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
>          * testsuite/gas/riscv/b-ext-64.d: Likewise.
>          * testsuite/gas/riscv/b-ext.s: Likewise.
>          * testsuite/gas/riscv/b-ext.d: Likewise.
> 
> include/
>          * opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
>          * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
> 
> opcodes/
>          * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
> 

I notice the xor vs xnor testsuite aspect pointed out in my
post from Jan 18th was addressed, but the other questions
remain:

For consistency with other insns taking immediate operands,
shouldn't slli.uw one have a sll.uw alias?

Also two perhaps more spec related questions: Why does slli.uw
allow for 7-bit wide shamt? Any shift count 32 and up is not
in need of this new insn, as slli will yield the same result.
(I could see the need in RV128, where counts up to 95 would be
needed, but right now talk is - I take it - mainly of RV32 and
RV64.)

The current draft also doesn't say anything about hints; one
could assume destination being x0 may get treated the same as
in the base spec, but in the absence of this being said
explicitly one could as well imply these are all simply
sort-of-nop-s, or even illegal.

Jan