[committed v2] RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.
Nelson Chu
nelson.chu@sifive.com
Fri Feb 19 04:02:48 GMT 2021
Hi Guys,
I notice that riscv sim also need to update the EXTRACT_UJTYPE_IMM and
EXTRACT_SBTYPE_IMM to EXTRACT_JTYPE_IMM and EXTRACT_BTYPE_IMM,
otherwise gdb build will fail. Fixed and committed.
Thanks
Nelson
On Fri, Feb 19, 2021 at 12:00 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
>
> [VALID/EXTRACT/ENCODE macros]
> BTYPE_IMM: Renamed from SBTYPE_IMM.
> JTYPE_IMM: Renamed from UJTYPE_IMM.
> CITYPE_IMM: Renamed from RVC_IMM.
> CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
> CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
> CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
> CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
> CIWTYPE_IMM: Renamed from RVC_UIMM8.
> CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
> CSSTYPE_IMM: Added for .insn without special encoding.
> CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
> CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
> CLTYPE_IMM: Added for .insn without special encoding.
> CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
> CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
> RVC_SIMM3: Unused and removed.
> CBTYPE_IMM: Renamed from RVC_B_IMM.
> CJTYPE_IMM: Renamed from RVC_J_IMM.
>
> * Added new operands and removed the unused ones,
>
> C5: Unsigned CL(CS) immediate, added for .insn directive.
> C6: Unsigned CSS immediate, added for .insn directive.
> Ci: Unused and removed.
> C<: Unused and removed.
>
> bfd/
> PR 27158
> * elfnn-riscv.c (perform_relocation): Updated encoding macros.
> (_bfd_riscv_relax_call): Likewise.
> (_bfd_riscv_relax_lui): Likewise.
> * elfxx-riscv.c (howto_table): Likewise.
> gas/
> PR 27158
> * config/tc-riscv.c (riscv_ip): Updated encoding macros.
> (md_apply_fix): Likewise.
> (md_convert_frag_branch): Likewise.
> (validate_riscv_insn): Likewise. Also arranged operands, including
> added C5 and C6 operands, and removed unused Ci and C< operands.
> * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
> * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
> * testsuite/gas/riscv/insn.s: Likewise.
> gdb/
> PR 27158
> * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
> (decode_j_type_insn): Likewise.
> (decode_cj_type_insn): Likewise.
> (decode_b_type_insn): Likewise.
> (decode): Likewise.
> include/
> PR 27158
> * opcode/riscv.h: Updated encoding macros.
> opcodes/
> PR 27158
> * riscv-dis.c (print_insn_args): Updated encoding macros.
> * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
> (match_c_addi16sp): Updated encoding macros.
> (match_c_lui): Likewise.
> (match_c_lui_with_hint): Likewise.
> (match_c_addi4spn): Likewise.
> (match_c_slli): Likewise.
> (match_slli_as_c_slli): Likewise.
> (match_c_slli64): Likewise.
> (match_srxi_as_c_srxi): Likewise.
> (riscv_insn_types): Added .insn css/cl/cs.
> sim/
> PR 27158
> * riscv/sim-main.c (execute_i): Updated encoding macros.
> ---
> bfd/ChangeLog | 8 ++
> bfd/elfnn-riscv.c | 34 ++++----
> bfd/elfxx-riscv.c | 10 +--
> gas/ChangeLog | 12 +++
> gas/config/tc-riscv.c | 181 +++++++++++++++++++++--------------------
> gas/doc/c-riscv.texi | 160 +++++++++++++++++++++---------------
> gas/testsuite/gas/riscv/insn.d | 26 +++---
> gas/testsuite/gas/riscv/insn.s | 24 ++++--
> gdb/ChangeLog | 9 ++
> gdb/riscv-tdep.c | 24 +++---
> include/ChangeLog | 5 ++
> include/opcode/riscv.h | 135 +++++++++++++++---------------
> opcodes/ChangeLog | 15 ++++
> opcodes/riscv-dis.c | 37 ++++-----
> opcodes/riscv-opc.c | 34 +++++---
> sim/ChangeLog | 5 ++
> sim/riscv/sim-main.c | 6 +-
> 17 files changed, 417 insertions(+), 308 deletions(-)
>
> diff --git a/bfd/ChangeLog b/bfd/ChangeLog
> index 0197e7b..7c7afe1 100644
> --- a/bfd/ChangeLog
> +++ b/bfd/ChangeLog
> @@ -1,3 +1,11 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * elfnn-riscv.c (perform_relocation): Updated encoding macros.
> + (_bfd_riscv_relax_call): Likewise.
> + (_bfd_riscv_relax_lui): Likewise.
> + * elfxx-riscv.c (howto_table): Likewise.
> +
> 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
>
> * Makefile.am: Added cpu-riscv.h.
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 8739673..ec8a3e7 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -1646,27 +1646,27 @@ perform_relocation (const reloc_howto_type *howto,
> break;
>
> case R_RISCV_JAL:
> - if (!VALID_UJTYPE_IMM (value))
> + if (!VALID_JTYPE_IMM (value))
> return bfd_reloc_overflow;
> - value = ENCODE_UJTYPE_IMM (value);
> + value = ENCODE_JTYPE_IMM (value);
> break;
>
> case R_RISCV_BRANCH:
> - if (!VALID_SBTYPE_IMM (value))
> + if (!VALID_BTYPE_IMM (value))
> return bfd_reloc_overflow;
> - value = ENCODE_SBTYPE_IMM (value);
> + value = ENCODE_BTYPE_IMM (value);
> break;
>
> case R_RISCV_RVC_BRANCH:
> - if (!VALID_RVC_B_IMM (value))
> + if (!VALID_CBTYPE_IMM (value))
> return bfd_reloc_overflow;
> - value = ENCODE_RVC_B_IMM (value);
> + value = ENCODE_CBTYPE_IMM (value);
> break;
>
> case R_RISCV_RVC_JUMP:
> - if (!VALID_RVC_J_IMM (value))
> + if (!VALID_CJTYPE_IMM (value))
> return bfd_reloc_overflow;
> - value = ENCODE_RVC_J_IMM (value);
> + value = ENCODE_CJTYPE_IMM (value);
> break;
>
> case R_RISCV_RVC_LUI:
> @@ -1679,12 +1679,12 @@ perform_relocation (const reloc_howto_type *howto,
> contents + rel->r_offset);
> insn = (insn & ~MATCH_C_LUI) | MATCH_C_LI;
> riscv_put_insn (howto->bitsize, insn, contents + rel->r_offset);
> - value = ENCODE_RVC_IMM (0);
> + value = ENCODE_CITYPE_IMM (0);
> }
> - else if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
> + else if (!VALID_CITYPE_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
> return bfd_reloc_overflow;
> else
> - value = ENCODE_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value));
> + value = ENCODE_CITYPE_LUI_IMM (RISCV_CONST_HIGH_PART (value));
> break;
>
> case R_RISCV_32:
> @@ -4139,7 +4139,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
> cause the PC-relative offset to later increase, so we need to add in the
> max alignment of any section inclusive from the call to the target.
> Otherwise, we only need to use the alignment of the current section. */
> - if (VALID_UJTYPE_IMM (foff))
> + if (VALID_JTYPE_IMM (foff))
> {
> if (sym_sec->output_section == sec->output_section
> && sym_sec->output_section != bfd_abs_section_ptr)
> @@ -4148,7 +4148,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
> }
>
> /* See if this function call can be shortened. */
> - if (!VALID_UJTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero))
> + if (!VALID_JTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero))
> return TRUE;
>
> /* Shorten the function call. */
> @@ -4157,7 +4157,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
> auipc = bfd_getl32 (contents + rel->r_offset);
> jalr = bfd_getl32 (contents + rel->r_offset + 4);
> rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
> - rvc = rvc && VALID_RVC_J_IMM (foff);
> + rvc = rvc && VALID_CJTYPE_IMM (foff);
>
> /* C.J exists on RV32 and RV64, but C.JAL is RV32-only. */
> rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
> @@ -4169,7 +4169,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
> auipc = rd == 0 ? MATCH_C_J : MATCH_C_JAL;
> len = 2;
> }
> - else if (VALID_UJTYPE_IMM (foff))
> + else if (VALID_JTYPE_IMM (foff))
> {
> /* Relax to JAL rd, addr. */
> r_type = R_RISCV_JAL;
> @@ -4298,8 +4298,8 @@ _bfd_riscv_relax_lui (bfd *abfd,
>
> if (use_rvc
> && ELFNN_R_TYPE (rel->r_info) == R_RISCV_HI20
> - && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
> - && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval)
> + && VALID_CITYPE_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
> + && VALID_CITYPE_LUI_IMM (RISCV_CONST_HIGH_PART (symval)
> + (link_info->relro ? 2 * ELF_MAXPAGESIZE
> : ELF_MAXPAGESIZE)))
> {
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index d3b882b..fd0fb49 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -235,7 +235,7 @@ static reloc_howto_type howto_table[] =
> "R_RISCV_BRANCH", /* name */
> FALSE, /* partial_inplace */
> 0, /* src_mask */
> - ENCODE_SBTYPE_IMM (-1U), /* dst_mask */
> + ENCODE_BTYPE_IMM (-1U), /* dst_mask */
> TRUE), /* pcrel_offset */
>
> /* 20-bit PC-relative jump offset. */
> @@ -250,7 +250,7 @@ static reloc_howto_type howto_table[] =
> "R_RISCV_JAL", /* name */
> FALSE, /* partial_inplace */
> 0, /* src_mask */
> - ENCODE_UJTYPE_IMM (-1U), /* dst_mask */
> + ENCODE_JTYPE_IMM (-1U), /* dst_mask */
> TRUE), /* pcrel_offset */
>
> /* 32-bit PC-relative function call (AUIPC/JALR). */
> @@ -659,7 +659,7 @@ static reloc_howto_type howto_table[] =
> "R_RISCV_RVC_BRANCH", /* name */
> FALSE, /* partial_inplace */
> 0, /* src_mask */
> - ENCODE_RVC_B_IMM (-1U), /* dst_mask */
> + ENCODE_CBTYPE_IMM (-1U), /* dst_mask */
> TRUE), /* pcrel_offset */
>
> /* 11-bit PC-relative jump offset. */
> @@ -674,7 +674,7 @@ static reloc_howto_type howto_table[] =
> "R_RISCV_RVC_JUMP", /* name */
> FALSE, /* partial_inplace */
> 0, /* src_mask */
> - ENCODE_RVC_J_IMM (-1U), /* dst_mask */
> + ENCODE_CJTYPE_IMM (-1U), /* dst_mask */
> TRUE), /* pcrel_offset */
>
> /* High 6 bits of 18-bit absolute address. */
> @@ -689,7 +689,7 @@ static reloc_howto_type howto_table[] =
> "R_RISCV_RVC_LUI", /* name */
> FALSE, /* partial_inplace */
> 0, /* src_mask */
> - ENCODE_RVC_IMM (-1U), /* dst_mask */
> + ENCODE_CITYPE_IMM (-1U), /* dst_mask */
> FALSE), /* pcrel_offset */
>
> /* GP-relative load. */
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index a90ab78..ae1bd92 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,15 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * config/tc-riscv.c (riscv_ip): Updated encoding macros.
> + (md_apply_fix): Likewise.
> + (md_convert_frag_branch): Likewise.
> + (validate_riscv_insn): Likewise. Also arranged operands, including
> + added C5 and C6 operands, and removed unused Ci and C< operands.
> + * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
> + * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
> + * testsuite/gas/riscv/insn.s: Likewise.
> +
> 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
>
> * config/tc-riscv.c: Included cpu-riscv.h.
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 44450d7..5f4f3ec 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -996,36 +996,37 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case 'C': /* RVC */
> switch (c = *p++)
> {
> - case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
> - case 'c': break; /* RS1, constrained to equal sp. */
> - case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
> - case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
> - case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
> - case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
> - case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
> - case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
> + case 'U': break; /* CRS1, constrained to equal RD. */
> + case 'c': break; /* CRS1, constrained to equal sp. */
> + case 'T': /* CRS2, floating point. */
> + case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
> + case 'S': /* CRS1S, floating point. */
> case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
> + case 'w': break; /* CRS1S, constrained to equal RD. */
> + case 'D': /* CRS2S, floating point. */
> case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
> - case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case 'w': break; /* RS1S, constrained to equal RD. */
> - case 'x': break; /* RS2S, constrained to equal RD. */
> - case 'z': break; /* RS2S, constrained to be x0. */
> - case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
> - case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
> - case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
> - case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
> - case 'U': break; /* RS1, constrained to equal RD. */
> - case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
> - case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
> - case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
> - case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
> - case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
> - case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
> - case 'F': /* RVC funct for .insn directive. */
> + case 'x': break; /* CRS2S, constrained to equal RD. */
> + case 'z': break; /* CRS2S, constrained to be x0. */
> + case '>': /* CITYPE immediate, compressed shift. */
> + case 'u': /* CITYPE immediate, compressed lui. */
> + case 'v': /* CITYPE immediate, li to compressed lui. */
> + case 'o': /* CITYPE immediate, allow zero. */
> + case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
> + case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
> + case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
> + case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
> + case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
> + case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
> + case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
> + case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
> + case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
> + /* CLTYPE and CSTYPE have the same immediate encoding. */
> + case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
> + case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
> + case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
> + case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
> + case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
> + case 'F': /* Compressed funct for .insn directive. */
> switch (c = *p++)
> {
> case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
> @@ -1051,34 +1052,36 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case ')': break;
> case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
> case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
> - case 'A': break;
> - case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
> - case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> - case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
> - case 'I': break;
> - case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
> - case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> - case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1);
> - /* Fall through. */
> - case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
> + case 'A': break; /* Macro operand, must be symbol. */
> + case 'B': break; /* Macro operand, must be symbol or constant. */
> + case 'I': break; /* Macro operand, must be constant. */
> + case 'D': /* RD, floating point. */
> case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
> - case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
> + case 'Z': /* RS1, CSR number. */
> + case 'S': /* RS1, floating point. */
> case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> + case 'U': /* RS1 and RS2 are the same, floating point. */
> + USE_BITS (OP_MASK_RS1, OP_SH_RS1);
> + /* Fall through. */
> + case 'T': /* RS2, floating point. */
> case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
> - case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
> + case 'R': /* RS3, floating point. */
> + case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
> + case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
> + case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
> case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
> case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
> - case 'o':
> + case 'o': /* ITYPE immediate, load displacement. */
> case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
> - case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
> - case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
> + case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
> + case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
> - case 'z': break;
> - case '[': break;
> - case ']': break;
> - case '0': break;
> - case '1': break;
> + case 'z': break; /* Zero immediate. */
> + case '[': break; /* Unused operand. */
> + case ']': break; /* Unused operand. */
> + case '0': break; /* AMO displacement, must to zero. */
> + case '1': break; /* Relaxation operand. */
> case 'F': /* Funct for .insn directive. */
> switch (c = *p++)
> {
> @@ -2078,82 +2081,83 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> || imm_expr->X_add_number <= 0
> || imm_expr->X_add_number >= 64)
> break;
> - ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
> rvc_imm_done:
> s = expr_end;
> imm_expr->X_op = O_absent;
> continue;
> - case '<':
> + case '5':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || imm_expr->X_add_number <= 0
> + || imm_expr->X_add_number < 0
> || imm_expr->X_add_number >= 32
> - || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> - case '8':
> + case '6':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> || imm_expr->X_add_number < 0
> - || imm_expr->X_add_number >= 256
> - || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
> + || imm_expr->X_add_number >= 64
> + || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> - case 'i':
> + case '8':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || imm_expr->X_add_number == 0
> - || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
> + || imm_expr->X_add_number < 0
> + || imm_expr->X_add_number >= 256
> + || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'j':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> || imm_expr->X_add_number == 0
> - || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'k':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'l':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'm':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
> + ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'n':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
> + ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'o':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> @@ -2161,47 +2165,46 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> /* C.addiw, c.li, and c.andi allow zero immediate.
> C.addi allows zero immediate as hint. Otherwise this
> is same as 'j'. */
> - || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
> break;
> - ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'K':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> || imm_expr->X_add_number == 0
> - || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
> + ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'L':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || imm_expr->X_add_number == 0
> - || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
> + ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'M':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
> + ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'N':
> if (riscv_handle_implicit_zero_offset (imm_expr, s))
> continue;
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> || imm_expr->X_op != O_constant
> - || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
> + || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
> break;
> ip->insn_opcode |=
> - ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
> + ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'u':
> p = percent_op_utype;
> @@ -2215,7 +2218,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> && (imm_expr->X_add_number <
> RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
> break;
> - ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
> goto rvc_imm_done;
> case 'v':
> if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
> @@ -3114,7 +3117,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
> /* Fill in a tentative value to improve objdump readability. */
> bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
> bfd_vma delta = target - md_pcrel_from (fixP);
> - bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
> + bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
> }
> break;
>
> @@ -3124,7 +3127,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
> /* Fill in a tentative value to improve objdump readability. */
> bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
> bfd_vma delta = target - md_pcrel_from (fixP);
> - bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
> + bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
> }
> break;
>
> @@ -3134,7 +3137,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
> /* Fill in a tentative value to improve objdump readability. */
> bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
> bfd_vma delta = target - md_pcrel_from (fixP);
> - bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
> + bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
> }
> break;
>
> @@ -3144,7 +3147,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
> /* Fill in a tentative value to improve objdump readability. */
> bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
> bfd_vma delta = target - md_pcrel_from (fixP);
> - bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
> + bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
> }
> break;
>
> @@ -3530,7 +3533,7 @@ md_convert_frag_branch (fragS *fragp)
> /* Invert the branch condition. Branch over the jump. */
> insn = bfd_getl16 (buf);
> insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
> - insn |= ENCODE_RVC_B_IMM (6);
> + insn |= ENCODE_CBTYPE_IMM (6);
> bfd_putl16 (insn, buf);
> buf += 2;
> goto jump;
> @@ -3557,7 +3560,7 @@ md_convert_frag_branch (fragS *fragp)
> /* Invert the branch condition. Branch over the jump. */
> insn = bfd_getl32 (buf);
> insn ^= MATCH_BEQ ^ MATCH_BNE;
> - insn |= ENCODE_SBTYPE_IMM (8);
> + insn |= ENCODE_BTYPE_IMM (8);
> bfd_putl32 (insn, buf);
> buf += 4;
>
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index e945482..c15297e 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -363,7 +363,7 @@ The pseudo la.tls.gd instruction can be expended to
> @cindex instruction formats, risc-v
> @cindex RISC-V instruction formats
>
> -The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
> +The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15
> instruction formats where some of the formats have multiple variants.
> For the @samp{.insn} pseudo directive the assembler recognizes some
> of the formats.
> @@ -394,6 +394,8 @@ only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
> @item simm12 @tab Sign-extended 12-bit immediate for operand x.
> @item simm20 @tab Sign-extended 20-bit immediate for operand x.
> @item simm6 @tab Sign-extended 6-bit immediate for operand x.
> +@item uimm5 @tab Unsigned 5-bit immediate for operand x.
> +@item uimm6 @tab Unsigned 6-bit immediate for operand x.
> @item uimm8 @tab Unsigned 8-bit immediate for operand x.
> @item symbol @tab Symbol or lable reference for operand x.
> @end multitable
> @@ -487,112 +489,136 @@ The following table lists the RISC-V instruction formats that are available
> with the @samp{.insn} pseudo directive:
>
> @table @code
> -@item R type: .insn r opcode, func3, func7, rd, rs1, rs2
> +@item R type: .insn r opcode6, func3, func7, rd, rs1, rs2
> @verbatim
> -+-------+-----+-----+-------+----+-------------+
> -| func7 | rs2 | rs1 | func3 | rd | opcode |
> -+-------+-----+-----+-------+----+-------------+
> -31 25 20 15 12 7 0
> ++-------+-----+-----+-------+----+---------+
> +| func7 | rs2 | rs1 | func3 | rd | opcode6 |
> ++-------+-----+-----+-------+----+---------+
> +31 25 20 15 12 7 0
> @end verbatim
>
> -@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
> -@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
> +@item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
> +@itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
> @verbatim
> -+-----+-------+-----+-----+-------+----+-------------+
> -| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
> -+-----+-------+-----+-----+-------+----+-------------+
> -31 27 25 20 15 12 7 0
> ++-----+-------+-----+-----+-------+----+---------+
> +| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
> ++-----+-------+-----+-----+-------+----+---------+
> +31 27 25 20 15 12 7 0
> @end verbatim
>
> -@item I type: .insn i opcode, func3, rd, rs1, simm12
> -@itemx I type: .insn i opcode, func3, rd, simm12(rs1)
> +@item I type: .insn i opcode6, func3, rd, rs1, simm12
> +@itemx I type: .insn i opcode6, func3, rd, simm12(rs1)
> @verbatim
> -+-------------+-----+-------+----+-------------+
> -| simm12 | rs1 | func3 | rd | opcode |
> -+-------------+-----+-------+----+-------------+
> -31 20 15 12 7 0
> ++--------------+-----+-------+----+---------+
> +| simm12[11:0] | rs1 | func3 | rd | opcode6 |
> ++--------------+-----+-------+----+---------+
> +31 20 15 12 7 0
> @end verbatim
>
> -@item S type: .insn s opcode, func3, rs2, simm12(rs1)
> +@item S type: .insn s opcode6, func3, rs2, simm12(rs1)
> @verbatim
> -+--------------+-----+-----+-------+-------------+-------------+
> -| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
> -+--------------+-----+-----+-------+-------------+-------------+
> -31 25 20 15 12 7 0
> ++--------------+-----+-----+-------+-------------+---------+
> +| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
> ++--------------+-----+-----+-------+-------------+---------+
> +31 25 20 15 12 7 0
> @end verbatim
>
> -@item B type: .insn s opcode, func3, rs1, rs2, symbol
> -@itemx SB type: .insn sb opcode, func3, rs1, rs2, symbol
> +@item B type: .insn s opcode6, func3, rs1, rs2, symbol
> +@itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol
> @verbatim
> -+------------+--------------+-----+-----+-------+-------------+-------------+--------+
> -| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
> -+------------+--------------+-----+-----+-------+-------------+-------------+--------+
> -31 30 25 20 15 12 7 0
> ++-----------------+-----+-----+-------+----------------+---------+
> +| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
> ++-----------------+-----+-----+-------+----------------+---------+
> +31 25 20 15 12 7 0
> @end verbatim
>
> -@item U type: .insn u opcode, rd, simm20
> +@item U type: .insn u opcode6, rd, simm20
> @verbatim
> -+---------------------------+----+-------------+
> -| simm20 | rd | opcode |
> -+---------------------------+----+-------------+
> -31 12 7 0
> ++--------------------------+----+---------+
> +| simm20[20|10:1|11|19:12] | rd | opcode6 |
> ++--------------------------+----+---------+
> +31 12 7 0
> @end verbatim
>
> -@item J type: .insn j opcode, rd, symbol
> -@itemx UJ type: .insn uj opcode, rd, symbol
> +@item J type: .insn j opcode6, rd, symbol
> +@itemx UJ type: .insn uj opcode6, rd, symbol
> @verbatim
> -+------------+--------------+------------+---------------+----+-------------+
> -| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
> -+------------+--------------+------------+---------------+----+-------------+
> -31 30 21 20 12 7 0
> ++------------+--------------+------------+---------------+----+---------+
> +| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
> ++------------+--------------+------------+---------------+----+---------+
> +31 30 21 20 12 7 0
> @end verbatim
>
> @item CR type: .insn cr opcode2, func4, rd, rs2
> @verbatim
> -+---------+--------+-----+---------+
> -| func4 | rd/rs1 | rs2 | opcode2 |
> -+---------+--------+-----+---------+
> -15 12 7 2 0
> ++-------+--------+-----+---------+
> +| func4 | rd/rs1 | rs2 | opcode2 |
> ++-------+--------+-----+---------+
> +15 12 7 2 0
> @end verbatim
>
> @item CI type: .insn ci opcode2, func3, rd, simm6
> @verbatim
> -+---------+-----+--------+-----+---------+
> -| func3 | imm | rd/rs1 | imm | opcode2 |
> -+---------+-----+--------+-----+---------+
> -15 13 12 7 2 0
> ++-------+----------+--------+------------+---------+
> +| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
> ++-------+----------+--------+------------+---------+
> +15 13 12 7 2 0
> @end verbatim
>
> -@item CIW type: .insn ciw opcode2, func3, rd, uimm8
> +@item CIW type: .insn ciw opcode2, func3, rd', uimm8
> @verbatim
> -+---------+--------------+-----+---------+
> -| func3 | imm | rd' | opcode2 |
> -+---------+--------------+-----+---------+
> -15 13 7 2 0
> ++-------+------------+-----+---------+
> +| func3 | uimm8[7:0] | rd' | opcode2 |
> ++-------+-------- ---+-----+---------+
> +15 13 5 2 0
> @end verbatim
>
> -@item CA type: .insn ca opcode2, func6, func2, rd, rs2
> +@item CSS type: .insn css opcode2, func3, rd, uimm6
> @verbatim
> -+---------+----------+-------+------+--------+
> -| func6 | rd'/rs1' | func2 | rs2' | opcode |
> -+---------+----------+-------+------+--------+
> -15 10 7 5 2 0
> ++-------+------------+----+---------+
> +| func3 | uimm6[5:0] | rd | opcode2 |
> ++-------+------------+----+---------+
> +15 13 7 2 0
> @end verbatim
>
> -@item CB type: .insn cb opcode2, func3, rs1, symbol
> +@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
> @verbatim
> -+---------+--------+------+--------+---------+
> -| func3 | offset | rs1' | offset | opcode2 |
> -+---------+--------+------+--------+---------+
> -15 13 10 7 2 0
> ++-------+------------+------+------------+------+---------+
> +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 |
> ++-------+------------+------+------------+------+---------+
> +15 13 10 7 5 2 0
> +@end verbatim
> +
> +@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
> +@verbatim
> ++-------+------------+------+------------+------+---------+
> +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
> ++-------+------------+------+------------+------+---------+
> +15 13 10 7 5 2 0
> +@end verbatim
> +
> +@item CA type: .insn ca opcode2, func6, func2, rd', rs2'
> +@verbatim
> ++-- ----+----------+-------+------+---------+
> +| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
> ++-------+----------+-------+------+---------+
> +15 10 7 5 2 0
> +@end verbatim
> +
> +@item CB type: .insn cb opcode2, func3, rs1', symbol
> +@verbatim
> ++-------+--------------+------+------------------+---------+
> +| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
> ++-------+--------------+------+------------------+---------+
> +15 13 10 7 2 0
> @end verbatim
>
> @item CJ type: .insn cj opcode2, symbol
> @verbatim
> -+---------+--------------------+---------+
> -| func3 | jump target | opcode2 |
> -+---------+--------------------+---------+
> -15 13 7 2 0
> ++-------+-------------------------------+---------+
> +| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
> ++-------+-------------------------------+---------+
> +15 13 2 0
> @end verbatim
>
>
> diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
> index 8f0badf..8cb3d64 100644
> --- a/gas/testsuite/gas/riscv/insn.d
> +++ b/gas/testsuite/gas/riscv/insn.d
> @@ -21,34 +21,40 @@ Disassembly of section .text:
> [^:]+: R_RISCV_JAL[ ]+target
> [^:]+:[ ]+fddff56f[ ]+jal[ ]+a0,0 \<target\>
> [^:]+: R_RISCV_JAL[ ]+target
> -[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
> [^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
> +[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
> [^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
> -[^:]+:[ ]+d9e9[ ]+beqz[ ]+a1,0 \<target\>
> +[^:]+:[ ]+c0aa[ ]+sw[ ]+a0,64\(sp\)
> +[^:]+:[ ]+41a8[ ]+lw[ ]+a0,64\(a1\)
> +[^:]+:[ ]+c1a8[ ]+sw[ ]+a0,64\(a1\)
> +[^:]+:[ ]+d5f1[ ]+beqz[ ]+a1,0 \<target\>
> [^:]+: R_RISCV_RVC_BRANCH[ ]+target
> -[^:]+:[ ]+bfc1[ ]+j[ ]+0 \<target\>
> +[^:]+:[ ]+b7e9[ ]+j[ ]+0 \<target\>
> [^:]+: R_RISCV_RVC_JUMP[ ]+target
> [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
> [^:]+:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
> [^:]+:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
> [^:]+:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
> -[^:]+:[ ]+fab50fe3[ ]+beq[ ]+a0,a1,0 \<target\>
> +[^:]+:[ ]+fab50ce3[ ]+beq[ ]+a0,a1,0 \<target\>
> [^:]+: R_RISCV_BRANCH[ ]+target
> -[^:]+:[ ]+fab50de3[ ]+beq[ ]+a0,a1,0 \<target\>
> +[^:]+:[ ]+fab50ae3[ ]+beq[ ]+a0,a1,0 \<target\>
> [^:]+: R_RISCV_BRANCH[ ]+target
> [^:]+:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
> [^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
> -[^:]+:[ ]+fafff56f[ ]+jal[ ]+a0,0 \<target\>
> +[^:]+:[ ]+fa9ff56f[ ]+jal[ ]+a0,0 \<target\>
> [^:]+: R_RISCV_JAL[ ]+target
> -[^:]+:[ ]+fabff56f[ ]+jal[ ]+a0,0 \<target\>
> +[^:]+:[ ]+fa5ff56f[ ]+jal[ ]+a0,0 \<target\>
> [^:]+: R_RISCV_JAL[ ]+target
> -[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
> [^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
> +[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
> [^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
> +[^:]+:[ ]+c0aa[ ]+sw[ ]+a0,64\(sp\)
> +[^:]+:[ ]+41a8[ ]+lw[ ]+a0,64\(a1\)
> +[^:]+:[ ]+c1a8[ ]+sw[ ]+a0,64\(a1\)
> [^:]+:[ ]+8d6d[ ]+and[ ]+a0,a0,a1
> -[^:]+:[ ]+ddd9[ ]+beqz[ ]+a1,0 \<target\>
> +[^:]+:[ ]+d9c9[ ]+beqz[ ]+a1,0 \<target\>
> [^:]+: R_RISCV_RVC_BRANCH[ ]+target
> -[^:]+:[ ]+bf71[ ]+j[ ]+0 \<target\>
> +[^:]+:[ ]+bf41[ ]+j[ ]+0 \<target\>
> [^:]+: R_RISCV_RVC_JUMP[ ]+target
> [^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
> [^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
> diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
> index 6c08f49..937ad11 100644
> --- a/gas/testsuite/gas/riscv/insn.s
> +++ b/gas/testsuite/gas/riscv/insn.s
> @@ -10,11 +10,14 @@ target:
> .insn uj 0x6f, a0, target
> .insn j 0x6f, a0, target
>
> - .insn ci 0x1, 0x0, a0, 4
> - .insn cr 0x2, 0x8, a0, a1
> + .insn cr 0x2, 0x8, a0, a1
> + .insn ci 0x1, 0x0, a0, 4
> .insn ciw 0x0, 0x0, a1, 1
> - .insn cb 0x1, 0x6, a1, target
> - .insn cj 0x1, 0x5, target
> + .insn css 0x2, 0x6, a0, 1
> + .insn cl 0x0, 0x2, a0, 1(a1)
> + .insn cs 0x0, 0x6, a0, 1(a1)
> + .insn cb 0x1, 0x6, a1, target
> + .insn cj 0x1, 0x5, target
>
> .insn r OP, 0, 0, a0, a1, a2
> .insn i OP_IMM, 0, a0, a1, 13
> @@ -27,12 +30,15 @@ target:
> .insn uj JAL, a0, target
> .insn j JAL, a0, target
>
> - .insn ci C1, 0x0, a0, 4
> - .insn cr C2, 0x8, a0, a1
> + .insn cr C2, 0x8, a0, a1
> + .insn ci C1, 0x0, a0, 4
> .insn ciw C0, 0x0, a1, 1
> - .insn ca C1, 0x23, 0x3, a0, a1
> - .insn cb C1, 0x6, a1, target
> - .insn cj C1, 0x5, target
> + .insn css C2, 0x6, a0, 1
> + .insn cl C0, 0x2, a0, 1(a1)
> + .insn cs C0, 0x6, a0, 1(a1)
> + .insn ca C1, 0x23, 0x3, a0, a1
> + .insn cb C1, 0x6, a1, target
> + .insn cj C1, 0x5, target
>
> .insn r MADD, 0, 0, a0, a1, a2, a3
> .insn r4 MADD, 0, 0, a0, a1, a2, a3
> diff --git a/gdb/ChangeLog b/gdb/ChangeLog
> index 0349d44..f608d9e 100644
> --- a/gdb/ChangeLog
> +++ b/gdb/ChangeLog
> @@ -1,3 +1,12 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
> + (decode_j_type_insn): Likewise.
> + (decode_cj_type_insn): Likewise.
> + (decode_b_type_insn): Likewise.
> + (decode): Likewise.
> +
> 2021-02-18 Tom Tromey <tom@tromey.com>
>
> * expression.h (struct expression) <evaluate>: Declare method.
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 460746a..7463b0c 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -1399,7 +1399,7 @@ class riscv_insn
> {
> m_opcode = opcode;
> m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
> - m_imm.s = EXTRACT_RVC_IMM (ival);
> + m_imm.s = EXTRACT_CITYPE_IMM (ival);
> }
>
> /* Helper for DECODE, decode 32-bit S-type instruction. */
> @@ -1449,14 +1449,14 @@ class riscv_insn
> {
> m_opcode = opcode;
> m_rd = decode_register_index (ival, OP_SH_RD);
> - m_imm.s = EXTRACT_UJTYPE_IMM (ival);
> + m_imm.s = EXTRACT_JTYPE_IMM (ival);
> }
>
> /* Helper for DECODE, decode 32-bit J-type instruction. */
> void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
> {
> m_opcode = opcode;
> - m_imm.s = EXTRACT_RVC_J_IMM (ival);
> + m_imm.s = EXTRACT_CJTYPE_IMM (ival);
> }
>
> void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
> @@ -1464,14 +1464,14 @@ class riscv_insn
> m_opcode = opcode;
> m_rs1 = decode_register_index (ival, OP_SH_RS1);
> m_rs2 = decode_register_index (ival, OP_SH_RS2);
> - m_imm.s = EXTRACT_SBTYPE_IMM (ival);
> + m_imm.s = EXTRACT_BTYPE_IMM (ival);
> }
>
> void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
> {
> m_opcode = opcode;
> m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
> - m_imm.s = EXTRACT_RVC_B_IMM (ival);
> + m_imm.s = EXTRACT_CBTYPE_IMM (ival);
> }
>
> /* Fetch instruction from target memory at ADDR, return the content of
> @@ -1629,31 +1629,31 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
> {
> m_opcode = ADDI;
> m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
> - m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
> + m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival);
> }
> else if (is_c_addi4spn_insn (ival))
> {
> m_opcode = ADDI;
> m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
> m_rs1 = RISCV_SP_REGNUM;
> - m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
> + m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival);
> }
> else if (is_c_lui_insn (ival))
> {
> m_opcode = LUI;
> m_rd = decode_register_index (ival, OP_SH_CRS1S);
> - m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
> + m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
> }
> /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
> and C_FSW is RV32 only. */
> else if (xlen != 4 && is_c_sd_insn (ival))
> - decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
> + decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival));
> else if (is_c_sw_insn (ival))
> - decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
> + decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival));
> else if (is_c_swsp_insn (ival))
> - decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
> + decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival));
> else if (xlen != 4 && is_c_sdsp_insn (ival))
> - decode_css_type_insn (SD, ival, EXTRACT_RVC_SDSP_IMM (ival));
> + decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival));
> /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
> So must try to match C_JR first as it ahs more bits in mask. */
> else if (is_c_jr_insn (ival))
> diff --git a/include/ChangeLog b/include/ChangeLog
> index 0f4936e..a24c920 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,3 +1,8 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * opcode/riscv.h: Updated encoding macros.
> +
> 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
>
> * opcode/riscv.h: Moved stuff and make the file tidy.
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 9372852..e790723 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -65,99 +65,106 @@ static const char * const riscv_pred_succ[16] =
> (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
> #define EXTRACT_STYPE_IMM(x) \
> (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
> -#define EXTRACT_SBTYPE_IMM(x) \
> +#define EXTRACT_BTYPE_IMM(x) \
> ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
> #define EXTRACT_UTYPE_IMM(x) \
> ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
> -#define EXTRACT_UJTYPE_IMM(x) \
> +#define EXTRACT_JTYPE_IMM(x) \
> ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
> -#define EXTRACT_RVC_IMM(x) \
> +#define EXTRACT_CITYPE_IMM(x) \
> (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
> -#define EXTRACT_RVC_LUI_IMM(x) \
> - (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
> -#define EXTRACT_RVC_SIMM3(x) \
> - (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
> -#define EXTRACT_RVC_UIMM8(x) \
> - (RV_X(x, 5, 8))
> -#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
> - ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
> -#define EXTRACT_RVC_ADDI16SP_IMM(x) \
> +#define EXTRACT_CITYPE_LUI_IMM(x) \
> + (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
> +#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
> ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
> -#define EXTRACT_RVC_LW_IMM(x) \
> - ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
> -#define EXTRACT_RVC_LD_IMM(x) \
> - ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
> -#define EXTRACT_RVC_LWSP_IMM(x) \
> +#define EXTRACT_CITYPE_LWSP_IMM(x) \
> ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
> -#define EXTRACT_RVC_LDSP_IMM(x) \
> +#define EXTRACT_CITYPE_LDSP_IMM(x) \
> ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
> -#define EXTRACT_RVC_SWSP_IMM(x) \
> +#define EXTRACT_CSSTYPE_IMM(x) \
> + (RV_X(x, 7, 6) << 0)
> +#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
> ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
> -#define EXTRACT_RVC_SDSP_IMM(x) \
> +#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
> ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
> -#define EXTRACT_RVC_B_IMM(x) \
> +#define EXTRACT_CIWTYPE_IMM(x) \
> + (RV_X(x, 5, 8))
> +#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
> + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
> +#define EXTRACT_CLTYPE_IMM(x) \
> + ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
> +#define EXTRACT_CLTYPE_LW_IMM(x) \
> + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
> +#define EXTRACT_CLTYPE_LD_IMM(x) \
> + ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
> +#define EXTRACT_CBTYPE_IMM(x) \
> ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
> -#define EXTRACT_RVC_J_IMM(x) \
> +#define EXTRACT_CJTYPE_IMM(x) \
> ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
>
> #define ENCODE_ITYPE_IMM(x) \
> (RV_X(x, 0, 12) << 20)
> #define ENCODE_STYPE_IMM(x) \
> ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
> -#define ENCODE_SBTYPE_IMM(x) \
> +#define ENCODE_BTYPE_IMM(x) \
> ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
> #define ENCODE_UTYPE_IMM(x) \
> (RV_X(x, 12, 20) << 12)
> -#define ENCODE_UJTYPE_IMM(x) \
> +#define ENCODE_JTYPE_IMM(x) \
> ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
> -#define ENCODE_RVC_IMM(x) \
> +#define ENCODE_CITYPE_IMM(x) \
> ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
> -#define ENCODE_RVC_LUI_IMM(x) \
> - ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
> -#define ENCODE_RVC_SIMM3(x) \
> - (RV_X(x, 0, 3) << 10)
> -#define ENCODE_RVC_UIMM8(x) \
> - (RV_X(x, 0, 8) << 5)
> -#define ENCODE_RVC_ADDI4SPN_IMM(x) \
> - ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
> -#define ENCODE_RVC_ADDI16SP_IMM(x) \
> +#define ENCODE_CITYPE_LUI_IMM(x) \
> + ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
> +#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
> ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
> -#define ENCODE_RVC_LW_IMM(x) \
> - ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
> -#define ENCODE_RVC_LD_IMM(x) \
> - ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
> -#define ENCODE_RVC_LWSP_IMM(x) \
> +#define ENCODE_CITYPE_LWSP_IMM(x) \
> ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
> -#define ENCODE_RVC_LDSP_IMM(x) \
> +#define ENCODE_CITYPE_LDSP_IMM(x) \
> ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
> -#define ENCODE_RVC_SWSP_IMM(x) \
> +#define ENCODE_CSSTYPE_IMM(x) \
> + (RV_X(x, 0, 6) << 7)
> +#define ENCODE_CSSTYPE_SWSP_IMM(x) \
> ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
> -#define ENCODE_RVC_SDSP_IMM(x) \
> +#define ENCODE_CSSTYPE_SDSP_IMM(x) \
> ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
> -#define ENCODE_RVC_B_IMM(x) \
> +#define ENCODE_CIWTYPE_IMM(x) \
> + (RV_X(x, 0, 8) << 5)
> +#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
> + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
> +#define ENCODE_CLTYPE_IMM(x) \
> + ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
> +#define ENCODE_CLTYPE_LW_IMM(x) \
> + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
> +#define ENCODE_CLTYPE_LD_IMM(x) \
> + ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
> +#define ENCODE_CBTYPE_IMM(x) \
> ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
> -#define ENCODE_RVC_J_IMM(x) \
> +#define ENCODE_CJTYPE_IMM(x) \
> ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
>
> #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
> #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
> -#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
> +#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
> #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
> -#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
> -#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
> -#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
> -#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
> -#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
> -#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
> -#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
> -#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
> -#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
> -#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
> -#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
> -#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
> -#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
> -#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
> -#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
> +#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
> +#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
> +#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
> + && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
> +#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
> + && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
> +#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
> +#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
> +#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
> +#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
> +#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
> +#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
> +#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
> +#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
> +#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
> +#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
> +#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
> +#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
>
> #define RISCV_RTYPE(insn, rd, rs1, rs2) \
> ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
> @@ -165,12 +172,12 @@ static const char * const riscv_pred_succ[16] =
> ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
> #define RISCV_STYPE(insn, rs1, rs2, imm) \
> ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
> -#define RISCV_SBTYPE(insn, rs1, rs2, target) \
> - ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
> +#define RISCV_BTYPE(insn, rs1, rs2, target) \
> + ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
> #define RISCV_UTYPE(insn, rd, bigimm) \
> ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
> -#define RISCV_UJTYPE(insn, rd, target) \
> - ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
> +#define RISCV_JTYPE(insn, rd, target) \
> + ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
>
> #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
> #define RVC_NOP MATCH_C_ADDI
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index 162aafcb..086dd33 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,3 +1,18 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * riscv-dis.c (print_insn_args): Updated encoding macros.
> + * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
> + (match_c_addi16sp): Updated encoding macros.
> + (match_c_lui): Likewise.
> + (match_c_lui_with_hint): Likewise.
> + (match_c_addi4spn): Likewise.
> + (match_c_slli): Likewise.
> + (match_slli_as_c_slli): Likewise.
> + (match_c_slli64): Likewise.
> + (match_srxi_as_c_srxi): Likewise.
> + (riscv_insn_types): Added .insn css/cl/cs.
> +
> 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
>
> * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 667dbd8..cc80d90 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -204,54 +204,51 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
> print (info->stream, "%s",
> riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
> break;
> - case 'i':
> - print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
> - break;
> case 'o':
> case 'j':
> - print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l));
> break;
> case 'k':
> - print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CLTYPE_LW_IMM (l));
> break;
> case 'l':
> - print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CLTYPE_LD_IMM (l));
> break;
> case 'm':
> - print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CITYPE_LWSP_IMM (l));
> break;
> case 'n':
> - print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CITYPE_LDSP_IMM (l));
> break;
> case 'K':
> - print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l));
> break;
> case 'L':
> - print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CITYPE_ADDI16SP_IMM (l));
> break;
> case 'M':
> - print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SWSP_IMM (l));
> break;
> case 'N':
> - print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
> + print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SDSP_IMM (l));
> break;
> case 'p':
> - info->target = EXTRACT_RVC_B_IMM (l) + pc;
> + info->target = EXTRACT_CBTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> break;
> case 'a':
> - info->target = EXTRACT_RVC_J_IMM (l) + pc;
> + info->target = EXTRACT_CJTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> break;
> case 'u':
> print (info->stream, "0x%x",
> - (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
> + (int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
> break;
> case '>':
> - print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
> + print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x3f);
> break;
> case '<':
> - print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
> + print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x1f);
> break;
> case 'T': /* Floating-point RS2. */
> print (info->stream, "%s",
> @@ -326,12 +323,12 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
> break;
>
> case 'a':
> - info->target = EXTRACT_UJTYPE_IMM (l) + pc;
> + info->target = EXTRACT_JTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> break;
>
> case 'p':
> - info->target = EXTRACT_SBTYPE_IMM (l) + pc;
> + info->target = EXTRACT_BTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> break;
>
> @@ -341,7 +338,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
> else if ((l & MASK_LUI) == MATCH_LUI)
> pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
> else if ((l & MASK_C_LUI) == MATCH_C_LUI)
> - pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
> + pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
> print (info->stream, "%s", riscv_gpr_names[rd]);
> break;
>
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 50a3f30..e0552db 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -73,7 +73,7 @@ const char * const riscv_fpr_names_abi[NFPR] =
> #define MASK_RD (OP_MASK_RD << OP_SH_RD)
> #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
> #define MASK_IMM ENCODE_ITYPE_IMM (-1U)
> -#define MASK_RVC_IMM ENCODE_RVC_IMM (-1U)
> +#define MASK_RVC_IMM ENCODE_CITYPE_IMM (-1U)
> #define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
> #define MASK_RM (OP_MASK_RM << OP_SH_RM)
> #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
> @@ -135,8 +135,7 @@ static int
> match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
> {
> return (match_opcode (op, insn)
> - && (((insn & MASK_RD) >> OP_SH_RD) == 2)
> - && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
> + && (((insn & MASK_RD) >> OP_SH_RD) == 2));
> }
>
> static int
> @@ -144,7 +143,7 @@ match_c_lui (const struct riscv_opcode *op, insn_t insn)
> {
> return (match_rd_nonzero (op, insn)
> && (((insn & MASK_RD) >> OP_SH_RD) != 2)
> - && EXTRACT_RVC_LUI_IMM (insn) != 0);
> + && EXTRACT_CITYPE_LUI_IMM (insn) != 0);
> }
>
> /* We don't allow lui zero,X to become a c.lui hint, so we need a separate
> @@ -155,13 +154,13 @@ match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn)
> {
> return (match_opcode (op, insn)
> && (((insn & MASK_RD) >> OP_SH_RD) != 2)
> - && EXTRACT_RVC_LUI_IMM (insn) != 0);
> + && EXTRACT_CITYPE_LUI_IMM (insn) != 0);
> }
>
> static int
> match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
> {
> - return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
> + return match_opcode (op, insn) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn) != 0;
> }
>
> /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
> @@ -169,7 +168,7 @@ match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
> static int
> match_c_slli (const struct riscv_opcode *op, insn_t insn)
> {
> - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
> + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
> }
>
> /* This requires a non-zero rd, and a non-zero shift. */
> @@ -177,7 +176,7 @@ match_c_slli (const struct riscv_opcode *op, insn_t insn)
> static int
> match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
> {
> - return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
> + return match_rd_nonzero (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
> }
>
> /* This requires a zero shift. A zero rd is a hint, so is allowed. */
> @@ -185,7 +184,7 @@ match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
> static int
> match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
> {
> - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
> + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) == 0;
> }
>
> /* This is used for both srli and srai. This requires a non-zero shift.
> @@ -194,7 +193,7 @@ match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
> static int
> match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
> {
> - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
> + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
> }
>
> const struct riscv_opcode riscv_opcodes[] =
> @@ -847,7 +846,6 @@ const struct riscv_opcode riscv_insn_types[] =
> {"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
> {"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
> {"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
> -
> {"b", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
> {"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
> {"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
> @@ -858,7 +856,6 @@ const struct riscv_opcode riscv_insn_types[] =
>
> {"uj", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 },
> {"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 },
> -
> {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 },
> {"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 },
>
> @@ -873,6 +870,19 @@ const struct riscv_opcode riscv_insn_types[] =
> {"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
> {"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
>
> +{"css", 0, INSN_CLASS_C, "O2,CF3,CV,C6", 0, 0, match_opcode, 0 },
> +{"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, match_opcode, 0 },
> +
> +{"cl", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 },
> +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 },
> +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 },
> +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 },
> +
> +{"cs", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 },
> +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 },
> +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 },
> +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 },
> +
> {"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 },
> {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 },
> {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 },
> diff --git a/sim/ChangeLog b/sim/ChangeLog
> index df11c5e..6bea868 100644
> --- a/sim/ChangeLog
> +++ b/sim/ChangeLog
> @@ -1,3 +1,8 @@
> +2021-02-19 Nelson Chu <nelson.chu@sifive.com>
> +
> + PR 27158
> + * riscv/sim-main.c (execute_i): Updated encoding macros.
> +
> 2021-02-13 Mike Frysinger <vapier@gentoo.org>
>
> * configure.tgt: Delete call to AC_SUBST(sim_arch).
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 8185bfc..ff328a0 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -157,7 +157,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
> unsigned_word u_imm = EXTRACT_UTYPE_IMM ((unsigned64) iw);
> unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
> - unsigned_word sb_imm = EXTRACT_SBTYPE_IMM (iw);
> + unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
> unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
> unsigned_word tmp;
> sim_cia pc = cpu->pc + 4;
> @@ -416,9 +416,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> break;
> case MATCH_JAL:
> TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name,
> - EXTRACT_UJTYPE_IMM (iw));
> + EXTRACT_JTYPE_IMM (iw));
> store_rd (cpu, rd, cpu->pc + 4);
> - pc = cpu->pc + EXTRACT_UJTYPE_IMM (iw);
> + pc = cpu->pc + EXTRACT_JTYPE_IMM (iw);
> TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
> break;
> case MATCH_JALR:
> --
> 2.7.4
>
More information about the Binutils
mailing list