your change "[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases"

[Jan Beulich]

Ramana,

with 2.36 I noticed

	st64bv	x0, x2, [x0]

triggering an "identical transfer and status registers". I realize
this operand combination is unpredictable, but for a different
reason (unless "transfer" is meant to cover both address _and_
destination registers). I notice further that your change
introduces ldxp tests, but aiui their operand combinations are
unpredictable for the latter and yet another reason. I found the
warning wording confusing, and I was able to understand what
exactly was wrong only after having dug out the respective doc
section. Looking more closely I believe all of the below are
affected:

	stlxr	w0, x2, [x0]
	stxr	w0, x2, [x0]
	st64bv	x0, x2, [x0]

	ldaxp	x0, x0, [x0]
	ldxp	x0, x0, [x0]


I also understand these should be warned about, but aren't:

	stlxp	w0, x2, x2, [x0]
	stxp	w0, x2, x2, [x0]

Furthermore I wonder whether

	st64bv	x2, x0, [x0]

isn't unpredictable, too - x2 is within the range of registers
loaded data would be written to.

Could all of this be consolidated?

Thanks, Jan