[GAS][AArch64] Define ETMv4 system registers

[Tamar Christina]

Hi Przemyslaw,

Thanks, these patches look good to me (but not a maintainer so you will still need approval).

That said could you add a NEWS entry for these and the TRBE and ETE registers?

Thanks,
Tamar

> -----Original Message-----
> From: Binutils <binutils-bounces@sourceware.org> On Behalf Of Przemyslaw
> Wirkus
> Sent: Thursday, September 24, 2020 4:10 PM
> To: binutils@sourceware.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Marcus Shawcroft
> <Marcus.Shawcroft@arm.com>; Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>
> Subject: [GAS][AArch64] Define ETMv4 system registers
> 
> This patch introduces ETMv4 (Embedded Trace Macrocell) system registers.
> 
> Note: With this patch system register s2_1_c0_c3_0 is disassembled now to
> trcstatr as they share same op0, op1, crn, crm, op2 (2, 1, 0, 3, 0) values.
> This change required a sysreg.d testcase update.
> 
> ETMv4 system registers are:
> - TRCACATRn a Trace Address Comparator Access Type Register [n=0-15].
> - TRCACVRn a Trace Address Comparator Value Register [n=0-15].
> - TRCAUTHSTATUS a Management Authentication Status register read-only
> register.
> - TRCAUXCTLR a Trace Auxiliary Control Register.
> - TRCBBCTLR a Trace Branch Broadcast Control Register.
> - TRCCCCTLR a Trace Cycle Count Control Register.
> - TRCCIDCCTLR0 a Trace Context ID Comparator Control Register 0.
> - TRCCIDCCTLR1 a Trace Context ID Comparator Control Register 1.
> - TRCCIDCVRn a Trace Context ID Comparator Value Register [n=0-7].
> - TRCCIDRn a Management Component ID0-ID3 Register read-only registers.
> - TRCCLAIMCLR a Trace Claim Tag Clear register.
> - TRCCLAIMSET a Trace Claim Tag Set register.
> - TRCCNTCTLRn a Trace Counter Control Register [n=0-3].
> - TRCCNTRLDVRn a Trace Counter Reload Value Register [n=0-3].
> - TRCCNTVRn a Trace Counter Value Register [n=0-3].
> - TRCCONFIGR a Trace Trace Configuration Register.
> - TRCDEVAFF0 a Management Device Affinity register 0 read-only register.
> - TRCDEVAFF1 a Management Device Affinity register 1 read-only register.
> - TRCDEVARCH a Management Device Architecture register read-only
> register.
> - TRCDEVID a Management Device ID register read-only register.
> - TRCDEVTYPE a Management Device Type register read-only register.
> - TRCDVCMRn a Trace Data Value Comparator Mask Register [n=0-7].
> - TRCDVCVRn a Trace Data Value Comparator Value Register [n=0-7].
> - TRCEVENTCTL0R a Trace Event Control 0 Register.
> - TRCEVENTCTL1R a Trace Event Control 1 Register.
> - TRCEXTINSELR a Trace External Input Select Register.
> - TRCIDR0 a Trace ID Register 0 read-only register.
> - TRCIDR1 a Trace ID Register 1 read-only register.
> - TRCIDR10 a Trace ID Register 10 read-only register.
> - TRCIDR11 a Trace ID Register 11 read-only register.
> - TRCIDR12 a Trace ID Register 12 read-only register.
> - TRCIDR13 a Trace ID Register 13 read-only register.
> - TRCIDR2 a Trace ID Register 2 read-only register.
> - TRCIDR3 a Trace ID Register 3 read-only register.
> - TRCIDR4 a Trace ID Register 4 read-only register.
> - TRCIDR5 a Trace ID Register 5 read-only register.
> - TRCIDR6 a Trace ID Register 6 read-only register.
> - TRCIDR7 a Trace ID Register 7 read-only register.
> - TRCIDR8 a Trace ID Register 8 read-only register.
> - TRCIDR9 a Trace ID Register 9 read-only register.
> - TRCIMSPEC0 a Trace IMPLEMENTATION DEFINED register 0.
> - TRCIMSPECn a Trace IMPLEMENTATION DEFINED register [n=1-7].
> - TRCITCTRL a Management Integration Mode Control register.
> - TRCLAR a Management Software Lock Access Register write-only register.
> - TRCLSR a Management Software Lock Status Register read-only register.
> - TRCOSLAR a Management OS Lock Access Register write-only register.
> - TRCOSLSR a Management OS Lock Status Register read-only register.
> - TRCPDCR a Management PowerDown Control Register.
> - TRCPDSR a Management PowerDown Status Register read-only register.
> - TRCPIDRn a Management Peripheral ID0-ID7 Register read-only registers.
> - TRCPRGCTLR a Trace Programming Control Register.
> - TRCPROCSELR a Trace PE Select Control Register.
> - TRCQCTLR a Trace Q Element Control Register.
> - TRCRSCTLRn a Trace Resource Selection Control Register [n=2-31].
> - TRCSEQEVRn a Trace Sequencer State Transition Control Registers.
> - TRCSEQRSTEVR a Trace Sequencer Reset Control Register.
> - TRCSEQSTR a Trace Sequencer State Register.
> - TRCSSCCRn a Trace Single-shot Comparator Control Register [n=0-7].
> - TRCSSCSRn a Trace Single-shot Comparator Status Register [n=0-7].
> - TRCSSPCICRn a Trace Single-shot PE Comparator Input Control Register
> [n=0-7].
> - TRCSTALLCTLR a Trace Stall Control Register.
> - TRCSTATR a Trace Status Register read-only register.
> - TRCSYNCPR a Trace Synchronization Period Register.
> - TRCTRACEIDR a Trace ID Register.
> - TRCTSCTLR a Trace Global Timestamp Control Register.
> - TRCVDARCCTLR a Trace ViewData Include/Exclude Address. Range
> Comparator
>   Control Register.
> - TRCVDCTLR a Trace ViewData Main Control Register.
> - TRCVDSACCTLR a Trace ViewData Include/Exclude Single. Address
> Comparator
>   Control Register.
> - TRCVICTLR a Trace ViewInst Main Control Register.
> - TRCVIIECTLR a Trace ViewInst Include/Exclude Control Register.
> - TRCVIPCSSCTLR a Trace ViewInst Start/Stop PE Comparator Control Register.
> - TRCVISSCTLR a Trace ViewInst Start/Stop Control Register.
> - TRCVMIDCCTLR0 a Trace Virtual context identifier Comparator Control
>   Register 0.
> - TRCVMIDCCTLR1 a Trace Virtual context identifier Comparator Control
>   Register 1.
> - TRCVMIDCVRn a Trace Virtual context identifier Comparator Value
>   Register [n=0-7].
> 
> Above system registers are documented here:
> https://developer.arm.com/documentation/ihi0064/latest
> 
> Note: as this is register only extension, we do not want to hide these
> registers behind -march flag going forward (they should be enabled by
> default).
> 
> aarch64-none-linux-gnu binutils regression tests OK.
> 
> OK for master branch?
> 
> PS: I do not have write permission, can this be commited in my name if
> approved please?
> 
> Kind regards,
> Przemyslaw Wirkus
> 
> gas/ChangeLog:
> 
> 2020-09-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
> 
>               * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
>               * testsuite/gas/aarch64/etm-ro-invalid.l: New test.
>               * testsuite/gas/aarch64/etm-ro-invalid.s: New test.
>               * testsuite/gas/aarch64/etm-ro.s: New test.
>               * testsuite/gas/aarch64/etm-wo-invalid.d: New test.
>               * testsuite/gas/aarch64/etm-wo-invalid.l: New test.
>               * testsuite/gas/aarch64/etm-wo-invalid.s: New test.
>               * testsuite/gas/aarch64/etm-wo.s: New test.
>               * testsuite/gas/aarch64/etm.s: New test.
>               * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0
> disassembled
>               now to trcstatr.
> 
> opcodes/ChangeLog:
> 
> 2020-09-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
> 
>               * aarch64-opc.c: Added ETMv4 system registers TRCACATRn,
> TRCACVRn,
>               TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR,
> TRCCIDCCTLR0, TRCCIDCCTLR1,
>               TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3,
> TRCCLAIMCLR, TRCCLAIMSET,
>               TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR,
> TRCDEVAFF0, TRCDEVAFF1,
>               TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn,
> TRCEVENTCTL0R,
>               TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3,
> TRCIDR4,
>               TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11,
> TRCIDR12,
>               TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR,
> TRCOSLAR
>               WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2,
> TRCPIDR3,
>               TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR,
> TRCRSCTLRn,
>               TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn,
> TRCSSPCICRn,
>               TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR,
> TRCVDARCCTLR,
>               TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR,
> TRCVISSCTLR,
>               TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.