[PATCH][GAS] aarch64: Limit Rt register number for LS64 load/store instructions

[Przemyslaw Wirkus]

Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and < 22):

    if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;

This patch adds check if Rt fulfils above requirement.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i

Regression tested and no issues.

OK for master?

gas/ChangeLog:

2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Rt_LS64.
	(parse_operands): Parse Rt range for AARCH64_OPND_Rt_LS64.
	* testsuite/gas/aarch64/ls64-invalid.l: Update test.
	* testsuite/gas/aarch64/ls64-invalid.s: Update test.
	* testsuite/gas/aarch64/ls64.s: Update test.

include/ChangeLog:

2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add new operand AARCH64_OPND_Rt_LS64.

opcodes/ChangeLog:

2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
	print.
	* aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
	Rt_ls64 operands.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
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