[PATCH 1/2] RISC-V: Don't generate the ELF privilege attributes when no CSR are used.
Nelson Chu
nelson.chu@sifive.com
Sat May 30 08:44:34 GMT 2020
gas/
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
---
gas/config/tc-riscv.c | 9 +++++++++
gas/testsuite/gas/riscv/attribute-01.d | 3 ---
gas/testsuite/gas/riscv/attribute-02.d | 3 ---
gas/testsuite/gas/riscv/attribute-03.d | 3 ---
gas/testsuite/gas/riscv/attribute-04.d | 3 ---
gas/testsuite/gas/riscv/attribute-06.d | 3 ---
gas/testsuite/gas/riscv/attribute-07.d | 3 ---
gas/testsuite/gas/riscv/attribute-08.d | 3 ---
gas/testsuite/gas/riscv/attribute-09.d | 3 ---
gas/testsuite/gas/riscv/attribute-10.d | 3 ---
gas/testsuite/gas/riscv/attribute-11.d | 8 ++++++++
gas/testsuite/gas/riscv/attribute-11.s | 1 +
gas/testsuite/gas/riscv/attribute-12.d | 9 +++++++++
gas/testsuite/gas/riscv/attribute-13.d | 6 ++++++
gas/testsuite/gas/riscv/attribute-unknown.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 2 --
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d | 3 ---
ld/testsuite/ld-riscv-elf/call-relax.d | 2 +-
25 files changed, 34 insertions(+), 57 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/attribute-11.d
create mode 100644 gas/testsuite/gas/riscv/attribute-11.s
create mode 100644 gas/testsuite/gas/riscv/attribute-12.d
create mode 100644 gas/testsuite/gas/riscv/attribute-13.d
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index da94b5b..cc77dbf 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -374,6 +374,9 @@ static bfd_boolean start_assemble = FALSE;
/* Indicate ELF attributes are explictly set. */
static bfd_boolean explicit_attr = FALSE;
+/* Indicate CSR are explictly used. */
+static bfd_boolean explicit_csr = FALSE;
+
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
@@ -2212,6 +2215,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'E': /* Control register. */
insn_with_csr = TRUE;
+ explicit_csr = TRUE;
if (reg_lookup (&s, RCLASS_CSR, ®no))
INSERT_OPERAND (CSR, *ip, regno);
else
@@ -3605,6 +3609,11 @@ riscv_write_out_attrs (void)
&& !riscv_set_default_priv_spec (NULL))
return;
+ /* If we already have set elf priv attributes, then generate them.
+ Otherwise, don't generate them when no CSR are used. */
+ if (!explicit_csr)
+ return;
+
/* Re-write priv attributes by default_priv_spec. */
priv_str = riscv_get_priv_spec_name (default_priv_spec);
p = priv_str;
diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index f027347..2e19e09 100644
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index 02b532d..ae0195e 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index ded529a..9916ff6 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index df6c818..408464d 100644
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
index e1d62c4..a2dd9fb 100644
--- a/gas/testsuite/gas/riscv/attribute-06.d
+++ b/gas/testsuite/gas/riscv/attribute-06.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
index 59f02b4..342a537 100644
--- a/gas/testsuite/gas/riscv/attribute-07.d
+++ b/gas/testsuite/gas/riscv/attribute-07.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d
index 13b82a9..c10ac0c 100644
--- a/gas/testsuite/gas/riscv/attribute-08.d
+++ b/gas/testsuite/gas/riscv/attribute-08.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32e1p9"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index 53945a2..cad1713 100644
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index 91691fd..ba903d1 100644
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-11.d b/gas/testsuite/gas/riscv/attribute-11.d
new file mode 100644
index 0000000..4bd66f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.d
@@ -0,0 +1,8 @@
+#as: -march-attr
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-11.s b/gas/testsuite/gas/riscv/attribute-11.s
new file mode 100644
index 0000000..81099b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.s
@@ -0,0 +1 @@
+ csrr a0, 0x0
diff --git a/gas/testsuite/gas/riscv/attribute-12.d b/gas/testsuite/gas/riscv/attribute-12.d
new file mode 100644
index 0000000..980b36c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-12.d
@@ -0,0 +1,9 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 9
+ Tag_RISCV_priv_spec_revision: 1
diff --git a/gas/testsuite/gas/riscv/attribute-13.d b/gas/testsuite/gas/riscv/attribute-13.d
new file mode 100644
index 0000000..b8dfe3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-13.d
@@ -0,0 +1,6 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d
index 120e3de..667f21a 100644
--- a/gas/testsuite/gas/riscv/attribute-unknown.d
+++ b/gas/testsuite/gas/riscv/attribute-unknown.d
@@ -4,8 +4,5 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
Tag_unknown_255: "test"
Tag_unknown_256: 123 \(0x7b\)
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 032f964..5baaba4 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 54a7621..a7d79a1 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 67f0437..d46dee8 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
index 5585fac..e4d965a 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -8,6 +8,4 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
index 91011a2..1039930 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
index 5bdea27..12ca1c4 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
index ac886fb..e41351d 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
index dd45f76..ac2a766 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
index ef0c154..608c05e 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 46d9c84..597ff67 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
#source: call-relax-1.s
#source: call-relax-2.s
#source: call-relax-3.s
-#as: -march=rv32ic
+#as: -march=rv32ic -mno-arch-attr
#ld: -melf32lriscv
#objdump: -d
#pass
--
2.7.4
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